Implant Activated Source/Drain Regions for Self-Aligned IGZO TFT

In this work, amorphous Indium Gallium Zinc Oxide (IGZO) TFTs with channel lengths scaled as small as L = 1 µm are presented which demonstrate excellent electrical characteristics, however the traditional metal-contact defined source/drain regions typically require several microns of gate overlap in order to provide ohmic behavior with minimal series resistance and ensure tolerance to overlay error. In addition, further scaling the channel length by simply reducing the source/drain metal gap is not feasible. The focus of this study is to investigate techniques to realize self-aligned (SA) IGZO TFTs that are not subject to gate-source/drain misalignment due to overlay error or process bias. Top gate (TG) co-planar and bottom gate (BG) staggered TFTs are fabricated using plasma immersion and ion implantation to selectively form conductive IGZO regions, with the channel region blocked by a gate-defined mask. Among the investigated treatments, oxygen plasma activation and ion implanted activation via 11B+ and 40Ar+ has been successfully demonstrated. Due to metal gate charging during ion implantation of SA-TG devices, the characteristics show a significant left-shift whereas SA-BG devices do not show this behavior. Electrical results suggest a defect-induced mechanism is involved with 40Ar+ implant activation of the S/D regions. However, 11B+ implant activation is attributed to the formation of an electrically active donor species involving chemical bonding. Both boron and argon demonstrate pronounced degradation in charge injection at higher dose treatments. Finally, a novel lithographic strategy which utilizes top-side flood exposure rather than a back-side through-glass exposure has also been explored, which would enable SA-BG devices on non-transparent substrates

Donor activation in boron and phosphorus implanted self-aligned bottom-gate Igzo Tfts

Self-aligned channel regions in thin-film transistors (TFTs) have advantages in reduced parasitic capacitance and stage delay, and a reduction in overhead real estate. A common method used to fabricate self-aligned a‑Si:H TFTs is to utilize a through-glass exposure of photoresist which is blocked by the opaque metal bottom-gate electrode [1,2]. This process does not require an additional photomask or lithographic alignment, and thus supports low production cost. Sputtered IGZO has been introduced into flat panel display product manufacturing, exhibiting a channel mobility of approximately an order of magnitude higher than a-Si:H. The working source/drain electrodes in IGZO TFTs can be direct metal contact regions to the IGZO, without the need for additional processes such as doping to render the IGZO conductive. Proper metallurgy and annealing processes can provide ohmic behavior with minimal series resistance, however this usually requires several microns of gate-to-source/drain overlap to ensure such behavior. Please click Download on the upper right corner to see the full abstract