Self-Timed Rings: A Promising Solution for Generating High-Speed High Resolution Low-Phase Noise Clocks

International audienceA high-speed multi-phase oscillator based on self-timed ring is proposed. Self-timed rings (STR) are promising approach for designing high-speed serial links and clock generators. Indeed, the architecture of STR allows us to achieve high frequencies with multiphase outputs and their oscillation frequency is not only depending on the number of stages but also on the initial state of the ring. Moreover, this architecture allows us 3 dB phase noise reduction when, while keeping the same frequency, when the stage number is doubled. In this chapter, we propose a method to design STR able to generate high-speed multi-phase outputs and we suggest a design flow for designing low-phase noise self-timed ring oscillators. A test chip has been designed and fabricated in STMicroelectonics CMOS65nm technology to verify the theoretical claims and validate the simulation results

Ring Oscillators : The Asynchronous Alternative

ISBN 978-1-61284-646-0International audienceSelf-timed rings (STR) are promising approach for designing high-speed serial links and clock generators. Indeed, the architecture of STRs presents well-suited characteristics for managing process variability and offering an appropriate structure to limit the phase noise. Therefore, STRs are considered as promising solution for generating Multiphase clocks. Moreover, Self-Timed Rings can easily be configured to change their frequency by controlling their initialization at reset time. A test chip has been designed and fabricated in STMicroelectonics CMOS65nm technology to verify the theoretical claims and validate the simulation results

Oscillation Period and Power Consumption in Configurable Self-Timed Rings Oscillators

International audienceA simple and accurate analytical model for evaluating the oscillation period of Self-timed rings is proposed. Thank to this model, the designer can easily choose the number of stages and the appropriate ring initialization. The model is so simple that it can quickly provide an estimation of the oscillation period only with a paper sheet and a pen. Nevertheless it takes into account analog effect called “Charlie effect”. The Charlie effect is of prime importance when modeling the behavior of synchronous rings. Moreover the relation between power consumption, ring initialization and stage implementation is showed. In order to validate our model, comparisons have been made with electrical simulations demonstrating the validity of our approach

A High-Speed High-Resolution Low-Phase Noise Oscillator Using Self-Timed Rings

International audienceA high-speed multi-phase oscillator based on self-timed ring is proposed. Self-timed rings (STR) are promising approach for designing high-speed serial links and clock generators. Indeed, the architecture of STR allows us to achieve high frequencies with multiphase outputs and their oscillation frequency is not only depending on the number of stages but also on the initial state of the ring. Moreover, this architecture allows us 3 dB phase noise reduction when, while keeping the same frequency, when the stage number is doubled .In this paper, we propose a method to design STR able to generate high-speed multi-phase outputs and we suggest a design flow for designing low-phase noise self-timed ring oscillators. All the electrical simulations and results have been performed using a CMOS 65nm technology from STMicroelectronics

Optimizing and Comparing CMOS Implementations of the C-element in 65nm technology: Self-Timed Ring Case

International audienceSelf-timed rings are a promising approach for designing high-speed serial links or clock generators. This study focuses on the ring stage components – a C-element and an inverter - and compares the performances of different implementations of this component in terms of speed, power consumption and phase noise. We also proposed a new self-timed ring stage - only composed by a C-element with complementary outputs - which allows us to increase the maximum speed of 25% and reduce the power consumption of 60% at the maximum frequency. All the electrical simulations and results have been performed using a CMOS 65nm technology from STMicroelectronics

A high-speed high-resolution low-phase noise oscillator using self-timed rings

International audienceA high-speed multi-phase oscillator based on self-timed ring is proposed. Self-timed rings (STR) are promising approach for designing high-speed serial links and clock generators. Indeed, the architecture of STR allows us to achieve high frequencies with multiphase outputs and their oscillation frequency is not only depending on the number of stages but also on the initial state of the ring. Moreover, this architecture allows us 3 dB phase noise reduction when, while keeping the same frequency, when the stage number is doubled .In this paper, we propose a method to design STR able to generate high-speed multi-phase outputs and we suggest a design flow for designing low-phase noise self-timed ring oscillators. All the electrical simulations and results have been performed using a CMOS 65nm technology from STMicroelectronics

Three-Point Modulator based on DPLL for Wideband Polar Modulation

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Optimizing and Comparing CMOS Implementations of the C-element in 65nm technology: Self-Timed Ring Case

ISBN :978-3-642-17751-4Self-timed rings are a promising approach for designing high-speed serial links or clock generators. This study focuses on the ring stage components – a C-element and an inverter - and compares the performances of different implementations of this component in terms of speed, power consumption and phase noise. We also proposed a new self-timed ring stage - only composed by a C-element with complementary outputs - which allows us to increase the maximum speed of 25% and reduce the power consumption of 60% at the maximum frequency. All the electrical simulations and results have been performed using a CMOS 65nm technology from STMicroelectronics

A novel High-Speed Multi-Phase Oscillator on Asynchronous Rings

International audienceA high-speed multi-phase oscillator based on self-timed ring is proposed. Self-Timed Rings (STR) are promising approach for designing high-speed serial links and clock generators. The architecture of STR allows us to achieve a maximum frequency with a multiphase outputs since the oscillation frequency is not only depending on the number of stages but on the number of “tokens” and “bubbles” circulating in the ring. In this paper, we propose a method to design STR able to generate high-speed multi-phase outputs. All the electrical simulations and results have been performed using a CMOS 65nm technology from STMicroelectronics