Statistical model for random telegraph noise in Flash memories

This paper presents a new physics-based statistical model for random telegraph noise in Flash memories. From the probabilistic superposition of elementary Markov processes describing the trapping/detrapping events taking place in the cell tunnel oxide, the model can explain the main features of the random telegraph noise threshold-voltage instability. The results on the statistical distribution of the threshold-voltage difference between two subsequent read accesses show good agreement between measurements and model predictions, even considering the time drift of the distribution tails. Moreover, the model gives a detailed spectroscopic analysis of the oxide defects responsible for the random telegraph noise, allowing a spatial and energetic localization of the traps involved in the threshold-voltage instability process

Program and SILC constraints on NC memories scaling: a Monte Carlo approach

We performed 3D Monte Carlo simulations of SOI NAND nanocrystal memories investigating the scaling constraints due to both program failure and reliability concerns. We show that the NC density should be optimized as a trade-off between number fluctuation and SILC immunity and that proper optimization is needed in order to meet the 45 nm ITRS node requirements

A Multi-Channel Low-Power System-on-Chip for in Vivo Recording and Wireless Transmission of Neural Spikes

This paper reports a multi-channel neural spike recording system-on-chip with digital data compression and wireless telemetry. The circuit consists of 16 amplifiers, an analog time-division multiplexer, a single 8 bit analog-to-digital converter, a digital signal compression unit and a wireless transmitter. Although only 16 amplifiers are integrated in our current die version, the whole system is designed to work with 64, demonstrating the feasibility of a digital processing and narrowband wireless transmission of 64 neural recording channels. Compression of the raw data is achieved by detecting the action potentials (APs) and storing 20 samples for each spike waveform. This compression method retains sufficiently high data quality to allow for single neuron identification (spike sorting). The 400 MHz transmitter employs a Manchester-Coded Frequency Shift Keying (MC-FSK) modulator with low modulation index. In this way, a 1:25 Mbit/s data rate is delivered within a limited band of about 3 MHz. The chip is realized in a 0:35 m AMS CMOS process featuring a 3 V power supply with an area of 3:1 2:7 mm2. The achieved transmission range is over 10 m with an overall power consumption for 64 channels of 17:2 mW. This figure translates into a power budget of 269 W per channel, in line with published results but allowing a larger transmission distance and more efficient bandwidth occupation of the wireless link. The integrated circuit was mounted on a small and light board to be used during neuroscience experiments with freely-behaving rats. Powered by 2 AAA batteries, the system can continuously work for more than 100 hours allowing for long-lasting neural spike recordings