Computation and Communication Optimization in Many-Core Heterogeneous Server-on-Chip

To make full use of parallelism of many cores in network-on-chip (NoC) based server-on-chip, this dissertation addresses the problem of computation and communication optimization during task-resource co-allocation of large-scale applications onto heterogeneous NoCs. Both static and dynamic task mapping and resource configuration have been performed while making the solution aware of power, thermal, dark/dim silicon, and capacity issues of chip. Our objectives are to minimize energy consumption and hotspots for improving NoC performance in terms of latency and throughput while meeting the above-mentioned chip constraints. Task-resource allocation and configuration problems have been formulated using linear programming (LP) optimization for optimal solutions. Due to high time complexity of LP solutions, fast heuristic approaches are proposed to get the near-optimal mapping and configuration solutions in a finite time for many-core systems. • We first present the hotspots minimization problems and solutions in NoC based many-core server-on-chip considering both computation and communication demands of the applications while meeting the chip constraints in terms of chip area budget, computational capacity of nodes, and communication capacity of links. • We then address power and thermal limitations in dark silicon era by proposing run-time resource management strategy and mapping for minimization of both hotspots and overall chip energy in many-core NoC. • We then present the power-thermal aware load-balanced mapping in heterogeneous CPU-GPU systems in many-core NoC. Distributed resource management strategy in CPU-GPU system using CPUs for system management and latency-sensitive tasks and GPUs for throughput-intensive tasks has been proposed. • We propose a neural network model to dynamically monitor, predict, and configure NoC resources. This work applies local and global neural networks classifiers for configuring NoC based on demands of applications and chip constraints. • Due to the integration of many-cores in a single chip, we propose express channels for improving NoC performance in terms of latency and throughput. We also propose mapping methodologies for efficient task-resource co-allocation in express channel enabled many-core NoC

Hydrobiology of Saline Agriculture Ecosystem: A Review of Scenario Change in South-West Region of Bangladesh

The aim of this review paper is to identify the production trends of shrimp and rice farming systems and associated hydrobiological parameters such as salinity in the coastal districts of Bangladesh. An intensive literature review has been conducted to explore salt stress-driven land use change, crop production, and changing ecosystem hydrobiology to adapt climate change impact from 2012–2022. The results indicate that a gradual extension of salt-driven land use and land cover (LULC) change has stressed agricultural production to a greater extent from 1973 to 2022 due to the high level of salinity. The unplanned expansion of shrimp culture is creating adverse consequences for the coastal ecosystem. Some suggestions have been proposed by analysing the mechanisms of crops’ response to salt stress, including several physiological, biochemical, and molecular bases to mitigate the adverse effects of salinity on agricultural production. Alternatively, prawn, shrimp, and crab have similar or slightly higher economic outputs, except for the crop-based agricultural system, which is highly affected by salinity rise. However, due to low input costs, low maintenance, and less environmental impact, farmers are shifting towards crab fattening and thus changing the hydrobiology of coastal land use and land cover

NeuroVP: A System-Level Virtual Platform for Integration of Neuromorphic Accelerators

Executing neural network (NN) applications on general-purpose processors result in a large power and performance overhead, due to the high cost of data movement between the processor and the main memory. Neuromorphic computing systems based on memristor crossbars, perform the NN main operation i.e., vector-matrix multiplications (VMM) in an efficient way in the analog domain. Thus, they circumvent the costly energy overhead of its digital counterpart. It can be expected that neuromorphic systems will be used initially as complements to current high-performance systems rather than as a replacement. This paper presents NeuroVP, a virtual platform integrating a neuromorphic accelerator, developed in SystemC that can model functionality, timing, and power consumption of the components integrating the system. Using NeuroVP to evaluate performance and power consumption at the electronic system level (ESL), it is corroborated that the execution of NN applications with a neuromorphic accelerator yields of up to 46x higher power efficiency and 26x speedup relative to a general-purpose computing system