First functionality tests of a 64 x 64 pixel DSSC sensor module connected to the complete ladder readout

The European X-ray Free Electron Laser (XFEL.EU) will provide every 0.1 s a train of 2700 spatially coherent ultrashort X-ray pulses at 4.5 MHz repetition rate. The Small Quantum Systems (SQS) instrument and the Spectroscopy and Coherent Scattering instrument (SCS) operate with soft X-rays between 0.5 keV - 6keV. The DEPFET Sensor with Signal Compression (DSSC) detector is being developed to meet the requirements set by these two XFEL.EU instruments. The DSSC imager is a 1 mega-pixel camera able to store up to 800 single-pulse images per train. The so-called ladder is the basic unit of the DSSC detector. It is the single unit out of sixteen identical-units composing the DSSC-megapixel camera, containing all representative electronic components of the full-size system and allows testing the full electronic chain. Each DSSC ladder has a focal plane sensor with 128 x 512 pixels. The read-out ASIC provides full-parallel readout of the sensor pixels. Every read-out channel contains an amplifier and an analog filter, an up-to 9 bit ADC and the digital memory. The ASIC amplifier have a double front-end to allow one to use either DEPFET sensors or Mini-SDD sensors. In the first case, the signal compression is a characteristic intrinsic of the sensor; in the second case, the compression is implemented at the first amplification stage. The goal of signal compression is to meet the requirement of single-photon detection capability and wide dynamic range. We present the first results of measurements obtained using a 64 x 64 pixel DEPFET sensor attached to the full final electronic and data-acquisition chain.Comment: Preprint proceeding for IWORID 2016, 18th International Workshop on Radiation Imaging Detectors, 3rd-7th July 2016, Barcelona, Spai

Developing a Monolithic Silicon Sensor in a 65 nm CMOS Imaging Technology for Future Lepton Collider Vertex Detectors

Monolithic CMOS sensors in a 65 nm imaging technology are being investigated by the CERN EP Strategic R&D Programme on Technologies for Future Experiments for an application in particle physics. The appeal of monolithic detectors lies in the fact that both sensor volume and readout electronics are integrated in the same silicon wafer, providing a reduction in production effort, costs and scattering material. The Tangerine Project WP1 at DESY participates in the Strategic R&D Programme and is focused on the development of a monolithic active pixel sensor with a time and spatial resolution compatible with the requirements for a future lepton collider vertex detector. By fulfilling these requirements, the Tangerine detector is suitable as well to be used as telescope planes for the DESY-II Test Beam facility. The project comprises all aspects of sensor development, from the electronics engineering and the sensor design using simulations, to laboratory and test beam investigations of prototypes. Generic TCAD Device and Monte-Carlo simulations are used to establish an understanding of the technology and provide important insight into performance parameters of the sensor. Testing prototypes in laboratory and test beam facilities allows for the characterization of their response to different conditions. By combining results from all these studies it is possible to optimize the sensor layout. This contribution presents results from generic TCAD and Monte-Carlo simulations, and measurements performed with test chips of the first sensor submission.Comment: 7 pages, 8 figures, submitted to IEEE Xplore as conference record for 2022 IEEE NSS/MIC/RTS

First functionality tests of a 64 x 64 pixel DSSC sensor module connected to the complete ladder readout

The European X-ray Free Electron Laser (XFEL.EU) will provide every 0.1 s a train of 2700 spatially coherent ultrashort X-ray pulses at 4.5 MHz repetition rate. The Small Quantum Systems (SQS) instrument and the Spectroscopy and Coherent Scattering instrument (SCS) operate with soft X-rays between 0.5 keV - 6keV. The DEPFET Sensor with Signal Compression (DSSC) detector is being developed to meet the requirements set by these two XFEL.EU instruments. The DSSC imager is a 1 mega-pixel camera able to store up to 800 single-pulse images per train. The so-called ladder is the basic unit of the DSSC detector. It is the single unit out of sixteen identical-units composing the DSSC-megapixel camera, containing all representative electronic components of the full-size system and allows testing the full electronic chain. Each DSSC ladder has a focal plane sensor with 128 x 512 pixels. The read-out ASIC provides full-parallel readout of the sensor pixels. Every read-out channel contains an amplifier and an analog filter, an up-to 9 bit ADC and the digital memory. The ASIC amplifier have a double front-end to allow one to use either DEPFET sensors or Mini-SDD sensors. In the first case, the signal compression is a characteristic intrinsic of the sensor; in the second case, the compression is implemented at the first amplification stage. The goal of signal compression is to meet the requirement of single-photon detection capability and wide dynamic range. We present the first results of measurements obtained using a 64 x 64 pixel DEPFET sensor attached to the full final electronic and data-acquisition chain

A 64-by-64 pixel-ADC matrix

An 8-bit 5-MS/s Wilkinson-type analog-to-digital converter (ADC) cell has been designed for parallel in-pixel digitization in a 64-by-64 pixel readout ASIC. Due to its simplicity, low power consumption, and small area requirement this type of ADC is suitable for pixel-level implementations. 720-ps time stamps are generated globally by means of 8-bit Gray-code counters. They are distributed column-wise to the pixel blocks together with a conversion-start signal along 13-mm long transmission lines. The analog input voltage is sampled-and-held on a capacitor. A pixel-internal current source is used to generate a voltage ramp. The conversion into a digital word is done when the ramp voltage equals the reference voltage, and the corresponding time stamp is latched. The ASIC is fabricated in IBM's 130-nm CMOS technology. The pixel-wise gain trimming properties provide a homogeneous gain distribution. Full matrix measurements demonstrate the achievement of a signal-to-noise ratio of 70 dB when all 4096 ADCs are working simultaneously. 75 % of the pixels show DNL better than 0.4 LSB, and the INL remains within ± 0.5 LSB for 99% of the pixels. The area and power dissipation of the in-pixel ADC amounts to 100 × 120 μm2 and 150 μW at 1.2-V power supply, respectively

Readout ASIC for fast digital imaging using SiPM sensors: Concept study

A novel digital imaging system using silicon-photomultiplier (SiPM) sensors is currently under development at DESY, Hamburg, for applications in high energy physics and photon science. The system is a hybrid based on a thinned SiPM-sensor chip from MPG-HLL, Munich. The final readout chip will comprise a 32-by-32 pixel matrix with 50-μm pitch and will be realized in IBMs 130-nm CMOS technology. It provides active quenching and recharging, fast and combinatorial trigger, time-to-digital converter, and fast readout of the pixel pattern at MHz-frame rates. A first prototype ASIC with 16-by-16 pixel matrix was designed including corresponding pixel electronics, fast trigger and single-row combinatorial trigger. Measurements on two samples of prototype ASIC give information about timing requirements. A TDC-bin width of ≤90 ps and a veto-time window of eight clock cycles are demanded. The maximal power consumption amounts to 15 μW per pixel at 1.2-V and 4 μW per pixel at 3.3-V supply voltage

A novel Silicon Photomultiplier with bulk integrated quench resistors: utilization in optical detection and tracking applications for particle physics

Silicon Photomultipliers (SiPMs) are a promising candidate for replacing conventional photomultiplier tubes (PMTs) in many applications, thanks to ongoing developments and advances in their technology. Conventional SiPMs are generally an array of avalanche photo diodes, operated in Geiger mode and read out in parallel, thus leading to the necessity of a high ohmic quenching resistor. This resistor enables passive quenching and is usually located on top of the array, limiting the fill factor of the device. In this paper, a novel detector concept with a bulk integrated quenching resistor will be recapped. In addition, due to other advantages of this novel detector design, a new concept, in which these devices will be utilized as tracking detectors for particle physics applications will be introduced, as well as first simulation studies and experimental measurements of this new approach