Study of Local Power Dissipation in Ultrascaled Silicon Nanowire FETs

The local electron power dissipation has been calculated in a field-effect nanowire transistor using a quantum transport formalism. Two different channel cross sections and optical and acoustic phonon mechanisms were considered. The phonon models used reproduce the phonon limited mobility in the cross sections studied. The power dissipation for different combinations of source, channel, and drain dimensions have been calculated. Due to the lack of complete electron energy relaxation inside the device, the Joule heat dissipation over-estimates the power dissipated in small nanotransistors. This over-estimation is larger for large cross sections due to the weaker phonon scattering. On the other hand, in narrow wires, the power dissipation inside the device can be large, therefore, mitigating against fabrication of very narrow nanowire transistors. We have also investigated the cooling of the device source region due to the mismatch of the Peltier coefficients between the source and the channel

Impact of phonon scattering in Si/GaAs/InGaAs nanowires and FinFets: a NEGF perspective

This paper reviews our previous theoretical studies and gives further insight into phonon scattering in 3D small nanotransistors using non-equilibrium Green function methodology. The focus is on very small gate-all-around nanowires with Si, GaAs or InGaAs cores. We have calculated phonon-limited mobility and transfer characteristics for a variety of cross-sections at low and high drain bias. The nanowire cross-sectional area is shown to have a significant impact on the phonon-limited mobility and on the current reduction. In a study of narrow Si nanowires we have examined the spatially resolved power dissipation and the validity of Joule’s law. Our results show that only a fraction of the power is dissipated inside the drain region even for a relatively large simulated length extension (approximately 30 nm). When considering large source regions in the simulation domain, at low gate bias, a slight cooling of the source is observed. We have also studied the impact of the real part of phonon scattering self-energy on a narrow nanowire transistor. This real part is usually neglected in nanotransistor simulation, whereas we compute its impact on current–voltage characteristic and mobility. At low gate bias, the imaginary part strongly underestimated the current and the mobility by 50 %. At high gate bias, the two mobilities are similar and the effect on the current is negligible

3-D Finite Element Monte Carlo Simulations of Scaled Si SOI FinFET With Different Cross Sections

Si SOI FinFETs with gate lengths of 12.8 nm and 10.7 nm are modelled using 3D Finite Element Monte Carlo (MC) simulations with 2D Schroedinger equation quantum corrections. These non-planar transistors are studied for two cross-sections: rectangular-like and triangular-like, and for two channel orientations: h100i and h110i. The 10.7 nm gate length rectangular-like FinFET is also simulated using the 3D Non-Equilibrium Green’s Functions (NEGF) technique and the results are compared with MC simulations. The 12.8 nm and 10.7 nm gate length rectangular-like FinFETs give larger drive currents per perimeter by about 25−27% than the triangular-like shaped but are outperformed by the triangular-like ones when normalised by channel area. The devices with a <100> channel orientation deliver a larger drive current by about 11% than their counterparts with a h110i channel when scaled to 12.8 nm and to 10.7 nm gate lengths. ID–VG characteristics at low and high drain biases obtained from the 3D NEGF simulations show a remarkable agreement with the MC results and overestimate the drain current from a gate bias of 0.5 V only due to exclusion of the interface roughness and ionized impurity scatterings

Study of Local Power Dissipation in Ultrascaled Silicon Nanowire FETs

Abstract-The local electron power dissipation has been calculated in a field-effect nanowire transistor using a quantum transport formalism. Two different channel cross sections and optical and acoustic phonon mechanisms were considered. The phonon models used reproduce the phonon limited mobility in the cross sections studied. The power dissipation for different combinations of source, channel, and drain dimensions have been calculated. Due to the lack of complete electron energy relaxation inside the device, the Joule heat dissipation over-estimates the power dissipated in small nanotransistors. This over-estimation is larger for large cross sections due to the weaker phonon scattering. On the other hand, in narrow wires, the power dissipation inside the device can be large, therefore, mitigating against fabrication of very narrow nanowire transistors. We have also investigated the cooling of the device source region due to the mismatch of the Peltier coefficients between the source and the channel