High Performance Multilayer Perceptron on a Custom Computing Machine

Multilayer perceptrons (MLPs) are one of the most popular neural network models for solving pattern classification and image classification problems. Because of their ability to learn complex decision boundaries, MLPs are used in many practical computer vision applications involving classification (or supervised segmentation). Once the connection weights in a MLP have been learnt, the network can be used repeatedly for classification of input test patterns. Several special-purpose architectures have been described in the literature for neural networks as they are slow on a conventional uniprocessor. In this paper, a high performance architecture for MLPs is presented using a novel class of hardware known as "custom computing machines". The main features of the proposed architecture are: (i) the number of nodes in a layer is not fixed; (ii) the number of layers in the network is not fixed; (iii) it is based on a set of reprogrammable FPGAs and a programmable crossbar; and (iv) it has a ..

High Performance Custom Computing for Image Segmentation

The use of dynamic instruction architectures based on field-programmable gate arrays (FPGAs) is described. Using this approach, an application specific instruction based system has been designed for image segmentation which is an important stage in a computer vision system. The specific application of interest here is texture-based page layout segmentation for document images. The complete segmentation algorithm has been designed for implementation on Splash 2 -- an attached processor (for SUN SPARCstations) based on Xilinx 4010 FPGAs. It is estimated that segmentation of a 1,024 \Theta 1,024 image will take less than 125 millisecond on a 16-board Splash 2 system compared to 250 seconds of CPU time on a SPARCstation 20. 1 Introduction The architecture of a general-purpose compute element is designed so that it provides a reasonable performance over a wide variety of applications. Even the newer processors supporting the latest architectural features such as superscalar, superpipelined..

Object Detection Using Gabor Filters

This paper pertains to the detection of objects located in complex backgrounds. A featurebased segmentation approach to the object detection problem is pursued, where the features are computed over multiple spatial orientations and frequencies. The method proceeds as follows: A given image is passed through a bank of even-symmetric Gabor filters. A selection of these filtered images is made and each (selected) filtered image is subjected to a nonlinear (sigmoidal like) transformation. Then, a measure of texture energy is computed in a window around each transformed image pixel. The texture energy ("Gabor features"), and their spatial locations, are inputted to a squared-error clustering algorithm. This clustering algorithm yields a segmentation of the original image -- it assigns to each pixel in the image a cluster label that identifies the amount of mean local energy the pixel possesses across different spatial orientations and frequencies. The method is applied to a number of visual..

Convolution on Splash 2

Convolution is a fundamental operation in many signal and image processing applications. Since the computation and communication pattern in a conuolu-tzon operation is regular, a number of specaal archttec-tures have been designed and implemented for this op-erator. The Von Neumann architectures cannot meet the real-time requirements of applications that use con-volution as an intermediate step. We combine the advantages of systolic algorithms with the low cost of developing application specific designs using field pro-grammable gate arrays (FPGAs) to buald a scalable convolver for use in computer vision systems. The performance of the systolic algorithm of Kung et al. [I] as compared theoretically and experimentally with many other convolution algorithms reported in the lit-erature. The implementation of a convolution opera-tion on Splash 2, an attached processor based on Xilinx 4010 FPGAs, is reported with impressive performance gains.