Optimization of single halo p-MOSFET implant parameters for improved analog performance and reliability

The effect of Channel Hot Carrier (CHC) stress under typical analog operating conditions is studied for p-MOSFETs. Our detailed characterization results show that Single Halo devices not only show improved performance, but also are immune to CHC degradation under various operating conditions

Morphology and Curie temperature engineering in crystalline La0.7Sr0.3MnO3 films on Si by pulsed laser deposition

Of all the colossal magnetoresistant manganites, La0.7Sr0.3MnO3 (LSMO) exhibits magnetic and electronic state transitions above room temperature, and therefore holds immense technological potential in spintronic devices and hybrid heterojunctions. As the first step towards this goal, it needs to be integrated with silicon via a well-defined process that provides morphology and phase control, along with reproducibility. This work demonstrates the development of pulsed laser deposition (PLD) process parameter regimes for dense and columnar morphology LSMO films directly on Si. These regimes are postulated on the foundations of a pressure-distance scaling law and their limits are defined post experimental validation. The laser spot size is seen to play an important role in tandem with the pressure-distance scaling law to provide morphology control during LSMO deposition on lattice-mismatched Si substrate. Additionally, phase stability of the deposited films in these regimes is evaluated through magnetometry measurements and the Curie temperatures obtained are 349 K (for dense morphology) and 355 K (for columnar morphology)-the highest reported for LSMO films on Si so far. X-ray diffraction studies on phase evolution with variation in laser energy density and substrate temperature reveals the emergence of texture. Quantitative limits for all the key PLD process parameters are demonstrated in order enable morphological and structural engineering of LSMO films deposited directly on Si. These results are expected to boost the realization of top-down and bottom-up LSMO device architectures on the Si platform for a variety of applications. (C) 2014 AIP Publishing LLC

The study of damage generation in n-channel MOS transistors operating in the substrate enhanced gate current regime

This paper analyzes in detail the damage generation in n-channel MOS transistors operating in the substrate enhanced gate current (SEGC) regime. The results are also compared with the damage generated during conventional hot carrier stress experiments. Stressing and charge pumping experiments are carried out to study the degradation with different substrate bias. Our results clearly show that the application of a substrate bias enhances degradation, which is strongly dependent on the transverse electric field and spread of the interface trap profile. The possible mechanisms responsible for such trends are discussed.© IEE

Dynamic Threshold voltage MOSFETs for future low power sub 1V CMOS applications

Threshold voltage scaling in deep sub-micron CMOS technologies is often dictated by the allowable off-state leakage currents and power dissipation. A recently proposed novel operation of a MOSFET is discussed in this paper, which is suitable for ultra low voltage operation (0.6 V or below) of ULSI circuits. In this mode of operation (referred to as Dynamic Threshold Voltage MOS, DTMOS), threshold voltage is made a function of gate voltage by tying the gate to the substrate of the MOSFET. Extensive comparisons are made in this work, using detailed device and circuit level simulations, on bulk DTMOS and conventional MOS structures. Our results show substantially higher drive currents and speeds for DTMOS operation, in comparison to the conventional MOSFET circuits, when the supply voltage is scaled below 1 V in the deep sub-micron technologies

Study of degradation in channel initiated secondary electron injection regime

This paper analyzes the Channel Initiated Secondary Electron injection mechanism and the resulting hot-carrier degradation in deep sub-micron n-channel MOSFETs. The correlation between gate (IG) and substrate current (IB) has been studied for different values of substrate bias. Stress and charge pumping measurements have been carried out to study the degradation under identical substrate bias and gate current conditions. Results show that under identical gate current (programming time for flash memory cells), the degradation is less for higher negative substrate bias.© IEE

Study of Degradation in Channel Initiated Secondary Electron Injection Regime

This paper analyzes the Channel Initiated Secondary Electron injection mechanism and the resulting hot-carrier degradation in deep sub-micron n-channel MOSFETs. The correlation between gate (I<SUB>G</SUB>) and substrate current (I<SUB>B</SUB>) has been studied for different values of substrate bias. Stress and charge pumping measurements have been carried out to study the degradation under identical substrate bias and gate current conditions. Results show that under identical gate current (programming time for flash memory cells), the degradation is less for higher negative substrate bias