Visual Fields at Presentation and after Trans-sphenoidal Resection of Pituitary Adenomas

Purpose: To evaluate visual field changes in patients with pituitary adenomas following trans-sphenoidal surgery. Methods: Eighteen patients with pituitary adenomas underwent a complete ophthalmic assessment and visual field analysis using the Humphrey Field Analyzer 30-2 program before and after trans-sphenoidal surgical resection at the Himalayan Institute of Medical Sciences over a one year period. Visual acuity, duration of symptoms, optic nerve head changes, pattern of visual field defects, and variables such as mean deviation and visual field index were compared. Results: Thirty-six eyes of 18 patients including 10 male and 8 female subjects with mean age of 35.1±9.9 years and histologically proven pituitary adenoma were included. Mean visual acuity at presentation was 0.29 logMAR which improved to 0.21 logMAR postoperatively (P = 0.305). Of 36 eyes, 24 (66.7%) had visual field defects including temporal defects in 12 eyes (33.3%), non-specific defects in 10 eyes (27.8%), and peripheral field constriction in 2 eyes (5.6%). Mean deviation of visual fields at presentation was -14.28 dB which improved to -11.32 dB postoperatively. The visual field index improved from 63.5% to 75% postoperatively. Favorable visual field outcomes were correlated with shorter duration of symptoms and absence of optic nerve head changes at presentation. Conclusion: Visual field defects were present in two thirds of patients at presentation. An overall improvement in vision and visual fields was noted after surgical resection. An inverse correlation was found between the duration of symptoms and postoperative visual field recovery, signifying the importance of early surgical intervention

A Graph Matching Based Integrated Scheduling Framework for Clustered VLIW Processors

Scheduling for clustered architectures involves spatial concerns (where to schedule) as well as temporal concerns (when to schedule) and various clustered VLIW configurations, connectivity types, and inter-cluster communication models present different performance trade-offs to a scheduler. The scheduler is responsible for resolving the conficting requirements of exploiting the parallelism offered by the hardware and limiting the communication among clusters to achieve better performance without stretching the overall schedule. This paper proposes a generic graph matching based framework that resolves the phase-ordering and fixedordering problems associated with scheduling on a clustered VLIW processor by simultaneously considering various scheduling alternatives of instructions. We observe approximately 16% and 28% improvement in the performance over an earlier integrated scheme and a phase-decoupled scheme respectively without extra code size enalty

Integrated Temporal and Spatial Scheduling for Extended Operand Clustered VLIW Processors

ILP Processors with centralized architecture are costly in terms of power, area and clock rate and are thus not suitable for consumer electronic devices. The consequence is the emergence of architectures having many interconnected clusters each with a separate register le and a few functional units. Among the many inter-cluster communication models proposed, the extended operand model extends some of operand elds of instruction with a cluster speci er and allows an instruction to read some of the operands from a different cluster without any extra cost. Scheduling for clustered processors involves spatial concerns (where to schedule) as well as temporal concerns (when to schedule). A scheduler is responsible for resolving the con icting requirements of aggressively exploiting the parallelism offered by hardware and limiting the communication among clusters to available slots. This paper proposes an integrated spatial and temporal scheduling algorithm for extended operand clustered VLIW processors and evaluates its effectiveness in improving the run time performance of the code without code size penalty

Compiler-assisted energy optimization for clustered VLIW processors

Clustered architecture processors are preferred for embedded systems because centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption. Although clustering helps by improving the clock speed, reducing the energy consumption of the logic, and making the design simpler, it introduces extra overheads by way of inter-cluster communication. This communication happens over long global wires having high load capacitance which leads to delay in execution and significantly high energy consumption. Inter-cluster communication also introduces many short idle cycles, thereby significantly increasing the overall leakage energy consumption in the functional units. The trend towards miniaturization of devices (and associated reduction in threshold voltage) makes energy consumption in interconnects and functional units even worse, and limits the usability of clustered architectures in smaller technologies. However, technological advancements now permit the design of interconnects and functional units with varying performance and power modes. In this paper, we propose scheduling algorithms that aggregate the scheduling slack of instructions and communication slack of data values to exploit the low-power modes of functional units and interconnects. Finally, we present a synergistic combination of these algorithms that simultaneously saves energy in functional units and interconnects to improves the usability of clustered architectures by achieving better overall energy-performance trade-offs. Even with conservative estimates of the contribution of the functional units and interconnects to the overall processor energy consumption, the proposed combined scheme obtains on average 8% and 10% improvement in overall energy-delay product with 3.5% and 2% performance degradation for a 2-clustered and a 4-clustered machine, respectively. We present a detailed experimental evaluation of the proposed schemes. Our test bed uses the Trimaran compiler infrastructure. (C) 2012 Elsevier Inc. All rights reserved

Exploring Energy-Performance Trade-offs for Heterogeneous Interconnect Clustered VLIW Processors

Clustered architecture processors are preferred for embedded systems because centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption. Although clustering helps by improving clock speed, reducing energy consumption of the logic, and making design simpler, it introduces extra overheads by way of inter-cluster communication. This communication happens over long global wires having high load capacitance which leads to delay in execution and significantly high energy consumption. Technological advancements permit design of a variety of clustered architectures by varying the degree of clustering and the type of interconnects. In this paper, we focus on exploring energy performance trade-offs in going from a unified VLIW architecture to different types of clustered VLIW architectures. We propose a new instruction scheduling algorithm that exploits scheduling slacks of instructions and communication slacks of data values together to achieve better energy-performance trade-offs for clustered architectures. Our instruction scheduling algorithm for clustered architectures with heterogeneous interconnect achieves 35 % and 40 % reduction in communication energy, whereas the overall energy-delay product improves by 4.5 % and 6.5 % respectively for 2 cluster and 4 cluster machines with marginal 1.6 % and 1.1 % increase in execution time. Our test bed uses the Trimaran compiler infrastructure

Criticality Driven Energy Aware Speculation for Speculative Multithreaded Processors

Speculative multithreaded architecture (SpMT) philosophy relies on aggressive speculative execution for improved performance. Aggressive speculative execution results in a significant wastage of dynamic energy due to useless computation in the event of mis-speculation. As energy consumption is becoming an important constraint in microprocessor design, it is extremely important to reduce such wastage of dynamic energy in SpMT processors in order to achieve a better performance to power ratio. Dynamic instruction criticality information can be effectively applied to control aggressive speculation in SpMT processors. In this paper, we present a model of micro-execution for SpMT processors to determine dynamic instruction criticality. We also present two novel techniques utilizing criticality information, namely delaying non-critical loads and criticality based thread-prediction for reducing useless computation and energy consumption. Our experiments show 17.71% and 11.63% reduction in dynamic energy for criticality based thread prediction and criticality based delayed load scheme respectively while the corresponding improvements in dynamic energy delay products are 13.93% and 5.54%

Criticality Based Speculation Control for Speculative Multithreaded Architectures

Unending quest for performance improvement coupled with the advancements in integrated circuit technology have led to the development of new architectural paradigm. Speculative multithreaded architecture (SpMT) philosophy relies on aggressive speculative execution for improved performance. However, aggressive speculative execution comes with a mixed flavor of improving performance, when successful, and adversely affecting the performance (and energy consumption) because of useless computation in the event of mis-speculation. Dynamic instruction criticality information can be applied to control and guide such an aggressive speculative execution.In this paper, we propose a model to determine the dynamic instruction criticality of SpMT execution. We have also developed two novel techniques, utilizing the criticality information, namely delaying the noncritical loads and the criticality based thread-prediction for reducing useless computations. Our experiments with criticality based speculation control show a significant reduction in useless computation with little reduction in speedup