AntiPlag: Plagiarism Detection on Electronic Submissions of Text Based Assignments

Plagiarism is one of the growing issues in academia and is always a concern in Universities and other academic institutions. The situation is becoming even worse with the availability of ample resources on the web. This paper focuses on creating an effective and fast tool for plagiarism detection for text based electronic assignments. Our plagiarism detection tool named AntiPlag is developed using the tri-gram sequence matching technique. Three sets of text based assignments were tested by AntiPlag and the results were compared against an existing commercial plagiarism detection tool. AntiPlag showed better results in terms of false positives compared to the commercial tool due to the pre-processing steps performed in AntiPlag. In addition, to improve the detection latency, AntiPlag applies a data clustering technique making it four times faster than the commercial tool considered. AntiPlag could be used to isolate plagiarized text based assignments from non-plagiarised assignments easily. Therefore, we present AntiPlag, a fast and effective tool for plagiarism detection on text based electronic assignments

Hardware accelerated protein inference framework

Protein inference plays a vital role in the proteomics study. Two major approaches could be used to handle the problem of protein inference; top-down and bottom-up. This paper presents a framework for protein inference, which uses hardware accelerated protein inference framework for handling the most important step in a bottom-up approach, viz. peptide identification during the assembling process. In our framework, identified peptides and their probabilities are used to predict the most suitable reference protein cluster for a given input amino acid sequence with the probability of identified peptides. The framework is developed on an FPGA where hardware software co-design techniques are used to accelerate the computationally intensive parts of the protein inference process. In the paper we have measured, compared and reported the time taken for the protein inference process in our framework against a pure software implementation

Hardware software co-design of the Aho-Corasick algorithm: Scalable for protein identification?

Pattern matching is commonly required in many application areas and bioinformatics is a major area of interest that requires both exact and approximate pattern matching. Much work has been done in this area, yet there is still a significant space for improvement in efficiency, flexibility, and throughput. This paper presents a hardware software co-design of Aho-Corasick algorithm in Nios II soft-processor and a study on its scalability for a pattern matching application. A software only approach is used to compare the throughput and the scalability of the hardware software co-design approach. According to the results we obtained, we conclude that the hardware software co-design implementation shows a maximum of 10 times speed up for pattern size of 1200 peptides compared to the software only implementation. The results also show that the hardware software co-design approach scales well for increasing data size compared to the software only approach

Integrated functions among multiple starch synthases determine both amylopectin chain length and branch linkage location in Arabidopsis leaf starch

This study assessed the impact on starch metabolism in Arabidopsis leaves of simultaneously eliminating multiple soluble starch synthases (SS) from among SS1, SS2, and SS3. Double mutant ss1- ss2- or ss1- ss3- lines were generated using confirmed null mutations. These were compared to the wild type, each single mutant, and ss1- ss2- ss3- triple mutant lines grown in standardized environments. Double mutant plants developed similarly to the wild type, although they accumulated less leaf starch in both short-day and long-day diurnal cycles. Despite the reduced levels in the double mutants, lines containing only SS2 and SS4, or SS3 and SS4, are able to produce substantial amounts of starch granules. In both double mutants the residual starch was structurally modified including higher ratios of amylose:amylopectin, altered glucan chain length distribution within amylopectin, abnormal granule morphology, and altered placement of α(1→6) branch linkages relative to the reducing end of each linear chain. The data demonstrate that SS activity affects not only chain elongation but also the net result of branch placement accomplished by the balanced activities of starch branching enzymes and starch debranching enzymes. SS3 was shown partially to overlap in function with SS1 for the generation of short glucan chains within amylopectin. Compensatory functions that, in some instances, allow continued residual starch production in the absence of specific SS classes were identified, probaby accomplished by the granule bound starch synthase GBSS1.ANR Génoplante GPLA0611GEuropean Union-FEDER, Région Nord Pas de Calais ARCir PlantTEQ5National Science Foundation DBI-0209789Comisión Interministerial de Ciencia y Tecnología BIO2009-07040Junta de Andalucía P09-CVI-470

Heterogeneous processor pipeline for a product cipher application

Processing data received as a stream is a task commonly performed by modern embedded devices, in a wide range of applications such as multimedia (encoding/decoding/ playing media), networking (switching and routing), digital security, scientific data processing, etc. Such processing normally tends to be calculation intensive and therefore requiring significant processing power. Therefore, hardware acceleration methods to increase the performance of such applications constitute an important area of study. In this paper, we present an evaluation of one such method to process streaming data, namely multi-processor pipeline architecture. The hardware is based on a Multiple-Processor System on Chip (MPSoC), using a data encryption algorithm as a case study. The algorithm is partitioned on a coarse grained level and mapped on to an MPSoC with five processor cores in a pipeline, using specifically configured Xtensa LX3 cores. The system is then selectively optimized by strengthening and pruning the resources of each processor core. The optimized system is evaluated and compared against an optimal single-processor System on Chip (SoC) for the same application. The multiple-processor pipeline system for data encryption algorithms used was observed to provide significant speed ups, up to 4.45 times that of the single-processor system, which is close to the ideal speed up from a five-stage pipeline