A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC with signal-independent delta-I noise DfT scheme

This paper presents a 3.5GSps 6-bit current-steering DAC with auxiliary circuitry to assist testing in a 1V digital 28nm CMOS process. The DAC uses only thin-oxide transistors and occupies 0.035mm2, making it suitable to embedding in VLSI systems, e.g. FPGA. To cope with the IC process variability, a unit element approach is generally employed. The 3 MSBs are implemented as 7 unary D/A cells and the 3 LSBs as 3 binary D/A cells, using appropriately reduced number of unit elements. Furthermore, all digital gates only make use of two basic unit blocks: a buffer and a multiplexer. For testing, a memory block of 5kbits is placed on-chip, which is externally loaded in a serial way but internally read in an 8x time-interleaved way. The memory is organized around 48 clocked 104-bit shift-registers. It keeps the resulting switching disturbances signal-independent and hence avoids inducing output non-linearity errors, even when a common power supply is shared with the DAC. This novelty allows reliable testing of the DAC core, while avoiding performance limitation risks of handling high-speed off-chip data streams. The DAC SFDR>40dB bandwidth is 0.8GHz, while the IM

Functionals of Brownian bridges arising in the current mismatch in D/A-converters

Digital-to-analog converters (DAC) transform signals from the abstract digital domain to the real analog world. In many applications, DAC’s play a crucial role. Due to variability in the production, various errors arise that influence the performance of the DAC. We focus on the current errors, which describe the fluctuations in the currents of the various unit current elements in the DAC. A key performance measure of the DAC is the Integrated Non-linearity (INL), which we study in this paper. There are several DAC architectures. The most widely used architectures are the ther-mometer, the binary and the segmented architectures. We study the two extreme architec-tures, namely, the thermometer and the binary architectures. We assume that the current errors are i.i.d. normally distributed, and reformulate the INL as a functional of a Brownian bridge. We then proceed by investigating these functionals. For the thermometer case, the functional is the maximal absolute value of the Brownian bridge, which has been investi-gated in the literature. For the binary case, we investigate properties of the functional, such as its mean, variance and density

Calibration of current-steering D/A Converters

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A 28-nm CMOS 7-GS/s 6-bit DAC with DfT clock and memory reaching SFDR >50 dB Up to 1 GHz

This brief presents a 7-GS/s 6-bit current-steering digital-to-analog converter (DAC) in 28-nm CMOS for VLSI System On Chip I/O embedding with an on-chip memory and clock generation circuits for wafer-sort testing. It demonstrates how Spurious Free Dynamic Range (>50) dB can be maintained up to 1 GHz, while keeping the DAC footprint small (-0.035) mm(^{mathrm {mathbf {2}}}). Several linearization techniques, such as current source cascodes with local biasing, thick-oxide output cascodes, bleeding currents, and 50% level of segmentation are validated for the first time at such very high frequencies. Testing is facilitated by means of integrating a digital front-end design-for-test scheme in 0.048 mm(^{mathrm {mathbf {2}}}). It uses a 5-kb 8X TI data memory, based on circular shift registers to avoid signal-dependent disturbances. An integrated 7-GHz Current Mode Logic ring oscillator-type clock generator and a serial data interface enable simple testing of the DAC at reduced cost

Integrated test support features for multi-GHz DACs in 28nm CMOS

This paper presents a 7GSps 6b current-steering DAC in 28nm CMOS for VLSI SoC embedding which includes on-chip memory and clock generation circuits for wafer-sort testing. Several linearization techniques are implemented to extend linearity to very high frequencies with levels of SFDR>50dB for signals up to 1GHz, while keeping the DAC footprint small - 0.035mm². Testing at full speed is facilitated by means of integrating a digital front-end BIST scheme in 0.048mm². It uses a 5kbit 8X TI data memory, based on circular shift registers to avoid signal-dependent disturbances. An integrated 7 GHz CML ring oscillator type clock generator, as well as a serial data interface, simplify and reduce the cost of testing the DAC at high-speed

A 28-nm CMOS 7-GS/s 6-bit DAC with DfT clock and memory reaching SFDR >50 dB Up to 1 GHz

This brief presents a 7-GS/s 6-bit current-steering digital-to-analog converter (DAC) in 28-nm CMOS for VLSI System On Chip I/O embedding with an on-chip memory and clock generation circuits for wafer-sort testing. It demonstrates how Spurious Free Dynamic Range (>50) dB can be maintained up to 1 GHz, while keeping the DAC footprint small (-0.035) mm(^{mathrm {mathbf {2}}}). Several linearization techniques, such as current source cascodes with local biasing, thick-oxide output cascodes, bleeding currents, and 50% level of segmentation are validated for the first time at such very high frequencies. Testing is facilitated by means of integrating a digital front-end design-for-test scheme in 0.048 mm(^{mathrm {mathbf {2}}}). It uses a 5-kb 8X TI data memory, based on circular shift registers to avoid signal-dependent disturbances. An integrated 7-GHz Current Mode Logic ring oscillator-type clock generator and a serial data interface enable simple testing of the DAC at reduced cost

Functionals of Brownian bridges arising in the current mismatch in D/A converters

Digital-to-analog converters (DAC) transform signals from the abstract digital domain to the real analog world. In many applications, DACs play a crucial role. Due to variability in the production, various errors arise that influence the performance of the DAC. We focus on the current errors, which describe the fluctuations in the currents of the various unit current elements in the DAC. A key performance measure of the DAC is the Integrated Nonlinearity (INL), which we study in this article. There are several DAC architectures. The most widely used architectures are the thermometer and the binary and the segmented architectures. We study the two extreme architectures, namely the thermometer and the binary architectures. We assume that the current errors are independent and identically normally distributed and reformulate the INL as a functional of a Brownian bridge. We then proceed by investigating these functionals. For the thermometer case, the functional is the maximal absolute value of the Brownian bridge, which has been investigated in the literature. For the binary case, we investigate properties of the functional, such as its mean, variance, and density