Toward an energy-efficient high-voltage compliant visual intracortical multichannel stimulator

ABSTRACT: We present, in this paper, a new multichip system aimed toward building an implantable visual intracortical stimulation device. The objective is to deliver energy-optimum pulse patterns to neural sites with needed compliance voltage across high electrode–tissue interface impedance of implantable microelectrodes. The first chip is an energy-efficient stimuli generator (SG), and the second one is a high-impedance microelectrode array driver (MED) output stage. The fourchannel SG produces rectangular, half-sine, plateau-sine, and other types of current pulse with stimulation current ranging from 2.32 to 220 μA per channel. The microelectrode array driver is able to deliver 20 V per anodic or cathodic phase across the microelectrode–tissue interface for ±13 V power supplies. The MED supplies different current levels with the maximum value of 400 μA per input and 100 μA per output channel simultaneously to 8–16 stimulation sites through microelectrodes, connected either in bipolar or monopolar configuration. Both chips receive power via inductive link and data through capacitive coupling. The SG and MED chips have been fabricated in 0.13-μm CMOS and 0.8-μm 5-/20-V CMOS/double-diffused metal-oxidesemiconductor technologies. The measured dc power budgets consumed by low- and mid-voltage chips are 2.56 and 2.1 mW consecutively. The system, modular in architecture, is interfaced with a newly developed platinum-coated pyramidal microelectrode array. In vitro test results with 0.9% phosphate buffer saline show the microelectrode impedance of 70 Ωk at 1 kHz

Placement Algorithm in Analog-layout Designs

Analog macrocell placement is an NP-hard problem. This paper presents an attempt to solve this problem by using the optimization flow of a genetic algorithm (GA) enhanced by simulated annealing (SA). The bit-matrix representation is employed to improve the search efficiency. In particular, to reduce the solution space without degrading search opportunities, the technique of cell slide is deployed to transform an absolute placement to a relative placement. Following this cell-slide process, it is proved that, for an initial placement, there always exists a solution that can guarantee no occurrence of overlaps among cells and meet any applicable symmetry constraints pertaining to analog layouts. For the optimization of the algorithm parameters, the fractional factorial experiment using an orthogonal array has been conducted, and the exact parameter values are determined using a meta-GA approach. The experimental results show that, compared with the SA approach, the proposed algorithm consumes less computation time while generating higher quality layouts, comparable to expert manual placement

Macro-cell Placement for Analog Physical Designs Using a Hybrid Genetic Algorithm with Simulated Annealing

Practical analog layout synthesis techniques have been the subject of active research for the past two decades to address the growing gap between the increasing chip functionality and the design productivity. In this paper, we present a novel macro-cell placement approach following the optimization flow of a genetic algorithm controlled by the methodology of simulated annealing. A process of cell slide is adopted to drastically reduce the configuration space without degrading search opportunities. In addition, this cell-slide process is used to satisfy the symmetry constraints essential for analog layouts. Furthermore, the dedicated cost function captures subtle electrical and geometrical constraints, such as area, net length, aspect ratio, proximity, parasitic effects, etc. required for analog layout and subsequent intellectual property reuse. To study the algorithm parameters, fractional factorial experiments and a meta-GA approach are employed. The proposed algorithm has been tested using several analog circuits. Compared to the simulated-annealing approach, the dominant one currently used for the analog placement problem, the proposed algorithm requires less computation time while generating higher quality layouts, comparable to expert manual placements. Furthermore, our hybrid algorithm and the method of parameter optimization can be readily adapted to different optimization problems across disciplines

A Hybrid Evolutionary Analogue Module Placement Algorithm for Integrated Circuit Layout Designs

This paper presents an integrated approach of simulated annealing (SA) and genetic algorithm (GA) for the analogue module placement in mixed-signal integrated circuit layout designs. The proposed algorithm follows the optimization flow of a normal GA controlled by the methodology of SA. The bit-matrix chromosomal representation is employed to describe the location and the orientation of modules. Compared with the conventional bit-string representation, the proposed chromosomal representation tends to significantly improve the search efficiency. In addition, a slide-based flat scheme is developed to transform an absolute co-ordinate placement of modules to a relative placement. In this way, the symmetry constraints imposed on analogue very large scale integration circuits can be easily fulfilled in the placement run. Use of a radiation-decoder can also drastically shrink the configuration space without degrading search opportunities. The proposed algorithm has been tested with several example circuits. The experiments show this promising algorithm makes the better performance than the simpler SA or GA approaches working alone, and the quality of the automatically generated layouts is comparable to those done manually

Toward an Energy-Efficient High-Voltage Compliant Visual Intracortical Multichannel Stimulator

ABSTRACT: We present, in this paper, a new multichip system aimed toward building an implantable visual intracortical stimulation device. The objective is to deliver energy-optimum pulse patterns to neural sites with needed compliance voltage across high electrode–tissue interface impedance of implantable microelectrodes. The first chip is an energy-efficient stimuli generator (SG), and the second one is a high-impedance microelectrode array driver (MED) output stage. The fourchannel SG produces rectangular, half-sine, plateau-sine, and other types of current pulse with stimulation current ranging from 2.32 to 220 μA per channel. The microelectrode array driver is able to deliver 20 V per anodic or cathodic phase across the microelectrode–tissue interface for ±13 V power supplies. The MED supplies different current levels with the maximum value of 400 μA per input and 100 μA per output channel simultaneously to 8–16 stimulation sites through microelectrodes, connected either in bipolar or monopolar configuration. Both chips receive power via inductive link and data through capacitive coupling. The SG and MED chips have been fabricated in 0.13-μm CMOS and 0.8-μm 5-/20-V CMOS/double-diffused metal-oxidesemiconductor technologies. The measured dc power budgets consumed by low- and mid-voltage chips are 2.56 and 2.1 mW consecutively. The system, modular in architecture, is interfaced with a newly developed platinum-coated pyramidal microelectrode array. In vitro test results with 0.9% phosphate buffer saline show the microelectrode impedance of 70 Ωk at 1 kHz

Different levels of single-strain probiotic (Bacillus subtilis) with proteolytic enzyme (serratiopeptidase) can be used as an alternative to antibiotic growth promoters in broiler

ABSTRACT: In the current study, the proteolytic enzyme (serratiopeptidase) was used to enhance the efficacy of Bacillus subtilis (B. subtilis) probiotic as a growth promotor in broiler chicken. The effects of serratiopeptidase on the efficacy of different levels of B. subtilis as a growth promotor in broiler chicks were evaluated regarding growth performance traits, villus histomorphometric characterization, and intestinal microbiota count. Day-old broiler chicks (n = 120) were allocated into 4 groups having 3 replicates/group. In the control group (C), the basal diet was kept without supplementation. In treatment groups (P100, P150, and P200), the basal diet was supplemented with 100, 150, and 200 mg probiotics, respectively besides 30 mg proteolytic enzyme in the 3 treated groups for 4 wk. The performance parameters were significantly affected by the supplementation of serratiopeptidase to the B. subtilis treatment groups. Feed intake (FI), body weight gain (WG), feed conversion ratio (FCR), and dressing percent were significantly improved in the treatment groups as compared to the control group. Significantly, the lowest feed intake was recorded for the P200 group. The highest body weight gain and dressing percentage were recorded for the P200 group. An improved FCR was recorded in the P200 group (1.7) as compared to the control group. The different levels of B. subtilis supplemented with serratiopeptidase revealed significant improvements (P<0.05) in the morphology of the intestine by showing increases in villus height and width and crypt depth of the small intestine. The microbial count revealed that E. coli and salmonella colonies were significantly reduced in the P200 group as compared to the control and other treatment groups. In conclusion, the supplementation of B. subtilis with serratiopeptidase as a growth promoter in broiler chicks significantly improved the overall performance, and intestinal health and reduced microbial load contributing to optimizing the performance of broiler chickens. The greatest improvement was observed in the P200 group fed with B. subtilis as a probiotic and serratiopeptidase enzyme (200 mg:30 mg)