51 research outputs found

    Compact modeling of subthreshold swing in double gate and nanowire MOSFETs, for Si and GaAs channel materials

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    International audienceIn this work, an analytical model for the subthreshold swing of double gate and cylindrical nanowire MOSFETs is proposed. Using the Voltage Doping Transform, it is shown that a one-dimensional potential model is sufficient to obtain a high accuracy, provided that an effective oxide thickness is used. The validity of this model is then confirmed with TCAD simulations. Finally, the impact of quantum effects is discussed. Based on Density-Gradient simulations of Si and GaAs MOSFETs, it is shown that the model is still valid when quantum effects are accounted for

    New Y -function based MOSFET parameter extraction method from weak to strong inversion range

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    International audienceA new Y-function based MOSFET parameter extraction method is proposed. This method relies on explicit expressions of inversion charge and drain current versus Yc(=Qi√Cgc)-function and Y(=Id/√gm)-function, respectively, applicable from weak to strong inversion range. It enables a robust MOSFET parameter extraction even for low gate voltage overdrive, whereas conventional extraction techniques relying on strong inversion approximation fail

    Compact modeling of the shift between classical and quantum threshold voltages in a III–V nanowire

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    International audienceIn this work, a quantum correction model for the threshold voltage of cylindrical nanowires is presented. Using a cylindrical self-consistent 1-D Poisson–Schrödinger (PS) numerical resolution of the charge profile as a reference, a generalized and compact Hänsch’s formula is proposed and systematically validated on simulation. As an example of application, this equation is then applied to III–V nanowires and to the study of the threshold voltage variability of these devices. The results suggest an increased variability due to the small mass of III–V semiconductors and to the larger quantum confinement of nanowire architectures. Previous articl

    Modeling of the impact of source/drain regions on short channel effects in MOSFETs

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