A new circuit technique for reduced leakage current in Deep Submicron CMOS technologies

Modern CMOS processes in the Deep Submicron regime are restricted to supply voltages below 2 volts and further to account for the transistors&apos; field strength limitations and to reduce the power per logic gate. To maintain the high switching performance, the threshold voltage must be scaled according with the supply voltage. However, this leads to an increased subthreshold current of the transistors in standby mode (<i>V</i>_<i>GS</i>=0). Another source of leakage is gate current, which becomes significant for gate oxides of 3nm and below. </p><p style=&quot;line-height: 20px;&quot;> We propose a <b>S</b>elf-<b>B</b>iasing <b>V</b>irtual <b>R</b>ails (SBVR) - CMOS technique which acts like an adaptive local supply voltage in case of standby mode. Most important sources of leakage currents are reduced by this technique. Moreover, SBVR-CMOS is capable of conserving stored information in sleep mode, which is vital for memory circuits. </p><p style=&quot;line-height: 20px;&quot;> Memories are exposed to radiation causing soft errors. This well-known problem becomes even worse in standby mode of typical SRAMs, that have low driving performance to withstand alpha particle hits. In this paper, a 16-transistor SRAM cell is proposed, which combines the advantage of extremely low leakage currents with a very high soft error stability

2.5 Gbps clock data recovery using 1/4th-rate quadricorrelator frequency detector and skew-calibrated multi-phase clock generator

A Gb/s clock and data recovery (CDR) circuit using 1/4th-rate digital quadricorrelator frequency detector and skew-calibrated multi-phase voltage-controlled oscillator is presented. With 1/4th-rate clock architecture, the coil-free oscillator can have lower operation frequency providing sufficient low-jitter operation. Moreover, it is an inherent 1-to-4 DEMUX. The skew calibration scheme is applied to reduce phase offset in multi-phase clock generator. The CDR with frequency detector can have small loop bandwidth, wide pull-in range and can operate without the need for a local reference clock. This 1/4th-rate CDR is implemented in standard 0.18 μm CMOS technology. It has an active area of 0.7 mm2 and consumes 100 mW at 1.8 V supply. The CDR has low jitter operation in a wide frequency range from 1&ndash;2.25 Gb/s. Measurement of Bit-Error Rate is less than 10&minus;12 for 2.25 Gb/s incoming data 27&minus;1 PRBS, jitter peak-to-peak of 0.7 unit interval (UI) modulation at 10 MHz

Design of UWB pulse radio transceiver using statistical correlation technique in frequency domain

In this paper, we propose a new technique to extract low power UWB pulse radio signals, near to noise level, using statistical correlation technique in frequency domain. The receiver consists of many narrow bandpass filters which extract energy either from transmitted UWB signal, interfering channels or noise. Transmitted UWB data can be eliminated by statistical correlation of multiple bandpass filter outputs. Super-regenerative oscillators, tuned within UWB spectrum, are designed as bandpass filters. Summers and comparators perform statistical correlation