Design of Asynchronous Circuits for High Soft Error Tolerance in Deep Submicron CMOS Circuits

As the devices are scaling down, the combinational logic will become susceptible to soft errors. The conventional soft error tolerant methods for soft errors on combinational logic do not provide enough high soft error tolerant capability with reasonably small performance penalty. This paper investigates the feasibility of designing quasi-delay insensitive (QDI) asynchronous circuits for high soft error tolerance. We analyze the behavior of null convention logic (NCL) circuits in the presence of particle strikes, and propose an asynchronous pipeline for soft-error correction and a novel technique to improve the robustness of threshold gates, which are basic components in NCL, against particle strikes by using Schmitt trigger circuit and resizing the feedback transistor. Experimental results show that the proposed threshold gates do not generate soft errors under the strike of a particle within a certain energy range if a proper transistor size is applied. The penalties, such as delay and power consumption, are also presented

Altar for a Future Love

A young person confesses their love for a future partner and takes a spiritual pilgrimage to Taipei. This hybrid fiction piece uses voice over, letter writing, and the gaze to communicate a contemporary experience with love

Barrier Synchronization Techniques For Distributed Process Creation

Synchronization techniques are proposed for algorithms which spawn processes remotely on loosely coupled processors based on run-time characteristics. The performance of the proposed synchronization schemes are measured on the iPSC/2 and SNAP-1 multiprocessors and their implementation cost is discussed. Results show that processes created dynamically throughout a distributed system can be synchronized at comparable overhead and cost to that required for fixed location process creation

A Device-Controlled Dynamic Configuration Framework Supporting Heterogeneous Resource Management

In this paper, a lightweight autonomous reconfiguration approach is developed for Field Programmable Gate Arrays (FPGAs). Under the Multilayer Runtime Reconfiguration Architecture (MRRA) paradigm, hardware configuration information is read and operated on directly at runtime to provide low overhead dynamic reconfiguration. This enables a standardized set of Application Programming Interfaces (APIs) for uniform access to heterogeneous logic and other resources. A prototype MRRA system is developed for Xilinx Virtex II Pro family of FPGAs to exercise partial reconfiguration capability. The Virtex II Pro On-Chip PowerPC core is used to control these reconfiguration protocols implemented in user logic. These two features make an autonomous reconfiguration system possible, allowing a FPGA to efficiently reconfigure itself under the control of a microprocessor core instantiated within the FPGA fabric

Helical latch for scalable Boolean logic operations

Nanomechanical computing elements which employ rotational symmetry and motion are designed and analyzed using a bounded continuum model. First, the Boolean logic functions of NOT, AND, OR, and XOR are realized using a helical latch, reset springs, and rod assemblies. Building upon these components, designs for shifters and two-level logic devices are developed. The helical latching mechanism calculates the Boolean output function as a positional displacement from a known reset state, which occurs exactly once during each 360 degrees instruction cycle. Operations of arbitrary word length can be performed by subdividing the logic disc into sectors where each sector operates on a single bit. Throughput can be increased by pipelining multiple-bit operands to yield a speedup which approaches a maximum value of (n+2) as compared to a single-level of non-pipelined logic with n inputs. Generally, speedup is bounded by (n+2)/p where p denotes the number of cycles between initiations of the pipe. An analysis of gate kinematics is performed to determine the device geometries and maximum operating frequencies for both non-pipelined and pipelined operation

A Device-Controlled Dynamic Configuration Framework Supporting Heterogeneous Resource Management

In this paper, a lightweight autonomous reconfiguration approach is developed for Field Programmable Gate Arrays (FPGAs). Under the Multilayer Runtime Reconfiguration Architecture (MRRA) paradigm, hardware configuration information is read and operated on directly at runtime to provide low overhead dynamic reconfiguration. This enables a standardized set of Application Programming Interfaces (APIs) for uniform access to heterogeneous logic and other resources. A prototype MRRA system is developed for Xilinx Virtex II Pro family of FPGAs to exercise partial reconfiguration capability. The Virtex II Pro On-Chip PowerPC core is used to control these reconfiguration protocols implemented in user logic. These two features make an autonomous reconfiguration system possible, allowing a FPGA to efficiently reconfigure itself under the control of a microprocessor core instantiated within the FPGA fabric

Self-Checking Fault Detection Using Discrepancy Mirrors

A method for robust detection of faults is developed based on pairwise parallel evaluation using Discrepancy Mirror logic. Discrepancy Mirrors provide coverage for the fault detector elements within the same mechanism used for the functional logic under test. The detector logic is self-testing and propagates functional outputs with adherence to a single fault-secure property so that erroneous outputs from any single fault are not propagated. Within the detector, bitwise equality comparisons are employed directly without additional data encoding/decoding schemes to determine the validity of the output. Fault handling is performed using the underlying data throughput so that additional test vectors are not required. The circuit was implemented for a Xilinx Virtex II Pro FPGA platform and fault-secure operation was verified using ModelSim-II for exhaustive stuck-at scenarios. Results indicate fault isolation in a pool of 100,000 resources using an expected value of 17.6 to 64-1pairings when as little as one half of the inputs applied articulate the fault

Self-timed architecture for masked successive approximation analog-to-digital conversion

In this paper, a novel architecture for self-timed analog-to-digital conversion is presented and designed using the NULL Convention Logic (NCL) paradigm. This analog-to-digital converter (ADC) employs successive approximation and a one-hot encoded masking technique to digitize analog signals. The architecture scales readily to any given resolution by utilizing the one-hot encoded scheme to permit identical logical components for each bit of resolution. The four-bit configuration of the proposed design has been implemented and assessed via simulation in 0.18-μm CMOS technology. Furthermore, the ADC may be interfaced with either synchronous or four-phase asynchronous digital systems. © World Scientific Publishing Company

Smart Priority Queue Algorithms For Self-Optimizing Event Storage

Low run-time overhead, self-adapting storage policies for priority queues called smart priority queue (SPQ) techniques are developed and evaluated. The proposed SPQ policies employ a low-complexity linear queue for near-head activities and a rapid-indexing variable bin-width calendar queue for distant events. The SPQ configuration is determined by monitoring queue access behavior using cost-scoring factors and then applying heuristics to adjust the organization of the underlying data structures. To illustrate and evaluate the method, an SPQ-based scheduler for discrete event simulation has been implemented and was used to assess the resulting efficiency, components of access time, and queue usage distributions of the existing and proposed algorithms. Results indicate that optimizing storage to the spatial distribution of queue access can decrease HOLD operation cost between 25% and 250% over existing algorithms such as calendar queues. © 2004 Elsevier B.V. All rights reserved