E-groups: a new technique for fast backward propagation in system-level test generation

ISBN: 0818674784This paper presents a new test pattern generation technique for complex systems. It focusses on test vector propagation through the individual blocks in the system. The technique is based on an easy identification of input-output pairs in each block. E (equality)-groups are formed for each block such that all the input vectors producing an identical output are grouped together. Such a grouping speeds up the task of backward propagation. In contrast to earlier methods, which considered the circuit structure for propagation, this method uses a functional approach and propagates the entire vector in one step. It is especially relevant to systems which consist of several blocks through which the test vector must be propagated. Results show that a significant reduction in the test generation time is possible

An Efficient Test Data Reduction Technique Through Dynamic Pattern Mixing Across Multiple Fault Models

Abstract: ATPG tool generated patterns are a major component of test data for large SOCs. With increasing sizes of chips, higher integration involving IP cores and the need for patterns targeting multiple fault models for better defect coverage in newer technologies, the issues of adequate coverage and reasonable test data volume and application time dominate the economics of test. We address the problem of generating compact set of test patterns across multiple fault models. Traditional approaches use separate ATPG for each fault models and minimize patterns either during pattern generation through static or dynamic compaction, or after pattern generation by simulating all patterns over all fault models for static compaction. We propose a novel ATPG technique where all fault models of interest are concurrently targeted in a single ATPG run. Patterns are generated in small intervals, each consisting of 16, 32 or 64 patterns. In each interval fault model specific ATPG setups generate separate pattern sets for their respective fault model. An effectiveness criterion then selects exactly one of those pattern sets. The selected set covers untargeted faults that would have required the most additional patterns. Pattern generation intervals are repeated until required coverage for faults of all models of interest is achieved. The sum total of all selected interval pattern sets is the overall test set for the DUT. Experiments on industrial circuits show pattern count reductions of 21 % to 68%. The technique is independent of any special ATPG tool or scan compression technique and requires no change or additional support in an existing ATPG system