Area Efficient Reconfigurable Buffer for NoC Router

Abstract In the current research, FPGA-based architecture of the Noc device reconfigurable router is suggested. Proposed router specification entry is done with the Verilog Hardware Description Language. The latest research has a five-channel router and a crossbar switch (east, west, north, south and local). Each channel has buffers and multiplexers. FIFO buffer stores data, and multiplexer monitors the input and output of data. The channel contains FIFO architecture and multiplexers. The crossbar switch is then planned and five other channels. Reducing the number of LUTs in the proposed work decreased the router area. A report is given for the number of LUTs used in a router. Results obtained indicate the area efficiency of the proposed router over existing method.</jats:p

Cascaded Multi-Level Inverter with APOD Based PV System for Induction Motor using DTFC Control

Abstract In this paper cascaded multi-level inverter based APOD control is designed to achieve harmonic reduction based on induction motor (IM) application which is fed by switched inductor quasi-Z source inverter (SL-qZSI) is proposed. The control method of proposed induction motor is controlled by direct torque and flux control (DTFC). The proposed converter qZSI is achieving the DC link voltage with improvement and to maintain the constant power supply. The proposed control technique for induction motor directs to reliability improvement and the capability of soft starting. The multi-level inverter with cascaded system is using with APOD control to reduce the total harmonic distortion in the supply voltage. The DTFC achieves the reduced settling time and stator inrush current reductions are achieved. The results and proposed system is analyzed and verified using MATLAB/Simulink environment.</jats:p

Design of New Reconfigurable Architecture for Implementing a Least Mean Square Finite Impulse Response Filter Using Borrow Select Subtraction (BSLS)

A design of reconfigurable architecture of FIR filter has been implemented using a Least Mean Square (LMS) adaptive filter. LMS adaptive filter is mainly sued for reducing the coefficients of the filter. Generally, a LMS filter contains normal adder, subtractor, mixer and a delay part. Most of the concepts deal with an adder namely Full Adder (FA), Ripple Carry Adder (RCA), Carry Select Adder (CSLA), etc., Instead of using CSLA; Borrow Select Subtractor (BSLS) is used in LMS filter architecture. By using BSLA LMS adaptive filter in a reconfigurable FIR filter architecture in the proposed scheme, the area, power and delay will be reduced. The proposed scheme achieves better performance when compared to an existing scheme. The proposed method is implemented in ModelSim tool and efficiency has been calculated by using the device Virtex 6 Low Power in Xilinx ISE Design Suite 12.4.</jats:p