RF modeling of FDSOI transistors using industry standard BSIM-IMG model

In this paper, RF modeling and step-by-step parameter extraction methodology of the BSIM-IMG model are discussed with experimental data. BSIM-IMG is the latest industry standard surface potential based model for fully depleted silicon-on-insulator (FDSOI) transistors. The impact of gate, substrate, and thermal networks is demonstrated with S-parameter data, which enable the BSIM-IMG model to capture RF behavior of the FDSOI transistor. The model is validated over a wide range of biases and frequencies and excellent agreement with the experimental data is obtained.7 page(s

Characterization of RF noise in UTBB FD-SOI MOSFET

In this paper, we report the noise measurements in the RF frequency range for ultrathin body and thin buried oxide fully depleted silicon on insulator (FD-SOI) transistors. We analyze the impact of back and front gate biases on the various noise parameters; along with discussions on the secondary effects in FD-SOI transistors which contribute to the thermal noise. Using calibrated TCAD simulations, we show that the noise figure changes with the substrate doping and buried oxide thickness.8 page(s

Analysis and modeling of flicker noise in lateral asymmetric channel MOSFETs

In this paper, flicker noise behavior of lateral non-uniformly doped MOSFET is studied using impedance field method. Our study shows that Klaassen Prins (KP) method, which forms the basis of noise model in MOSFETs, underestimates flicker noise in such devices. The same KP method overestimates thermal noise by 2–3 orders of magnitude in similar devices as demonstrated in Roy et al. (2007). This apparent discrepancy between thermal and flicker noise behavior lies in origin of these noises, which leads to opposite trend of local noise power spectral density vs doping. We have modeled the physics behind such behavior, which also explain the trends observed in the measurements (Agarwal et al., 2015).6 page(s

Modeling of GaN-based normally-off FinFET

In this letter, a macromodel for normally-off (enhancement mode) AlGaN/GaN-based FinFET (2-DEG channel at top with two MOS like sidewall channels) is proposed. AlGaN/GaN-based FinFET devices have improved gate control on the channel due to additional sidewall gates compared with planar structures, but device characteristics exhibit strong nonlinear dependence on fin-width. The proposed model captures both 2-DEG and sidewall channel conduction as well as the fin-width dependency on device characteristics. Model shows excellent agreement with state-of-the-art experimental data.3 page(s

Thermal resistance modeling in FDSOI transistors with industry standard model BSIM-IMG

The channel in Fully Depleted Silicon On Insulator (FDSOI) transistors is completely isolated from the substrate via buried oxide (BOX) and from the sides by shallow trench isolations, which results in high thermal resistance (Rth). Further, Rth increases with reduction in channel length (Lg). In this paper, we have proposed a compact model for the geometry and temperature dependence of Rth in FDSOI transistors. The model is validated against experimental and Technology Computer Aided Design (TCAD) data. The proposed model is implemented in the independent multi-gate model (BSIM-IMG) for FDSOI transistors.6 page(s

Modeling of nonlinear thermal resistance in FinFETs

In this paper, self-consistent three-dimensional (3D) device simulations for exact analysis of thermal transport in FinFETs are performed. We analyze the temperature rise in FinFET devices with the variation in the number of fins (N fin), shape of fins and fin pitch (F pitch). We investigate that the thermal resistance R th has nonlinear dependency on N fin and F pitch. We formulate a model for thermal resistance behavior correctly with N fin and F pitch variation. The proposed formulation is implemented in industry standard Berkeley short-channel independent gate FET model for common multi-gate transistors (BSIM-CMG) and validated with both experimental data and TCAD simulations.5 page(s

Analytical modeling and experimental validation of threshold voltage in BSIM6 MOSFET model

In this paper, an analytical model of threshold voltage for bulk MOSFET is developed. The model is derived from the physical charge-based core of BSIM6 MOSFET model, taking into account short channel effects, and is intended to be used in commercial SPICE simulators for operating point information. The model is validated with measurement data from IBM 90-nm technology node using various popular threshold voltage extraction techniques, and good agreement is obtained.4 page(s

Unified compact model covering drift-diffusion to ballistic carrier transport

In this letter, we present a unified compact model, which accurately captures carrier transport from the drift-diffusion to ballistic regime. This is a single unified model, which accounts for carrier degeneracy effects in ballistic transport. The model is implemented into the industry standard compact models for FinFETs, fully depleted silicon-on-insulator (FDSOI) devices and bulk MOSFETs: 1) Berkeley Spice model for common multi-gate; 2) Berkeley Spice model for independent multi-gate; and 3) BSIM6. The model is validated with experimental data and TCAD simulations for FDSOI devices, FinFETs, and bulk MOSFETs.4 page(s

Modeling the impact of substrate depletion in FDSOI MOSFETs

In this work, we have modeled the impact of substrate depletion in fully-depleted silicon-on-insulator (FDSOI) transistor and have extensively verified the model for both NMOS and PMOS with geometrical and temperature scaling. The model has an accurate behavior for C–V and I–V characteristics and preserves the smooth behavior of the high order derivatives. Model validation is done at 50 nm technology node with state of the art FDSOI transistors provided by Low-power Electronics Association and Project (LEAP) and excellent agreement with the experimental data is achieved after parameter extraction.6 page(s