Incremental Evaluation of Complex Conditions

Evaluating a complex condition such as users who have visited a certain type of website in the last week requires a great deal of processing power. The present disclosure describes an incremental evaluation technique that makes use of shortcuts and intermediate results in order to reduce the amount of time and processing needed to produce a final result. The main component of a visitor condition as described is a unified segment which can contain any number of simple or sequence type segment filters. Each segment filter can be evaluated using shortcuts and intermediate results. The evaluation of the entire unified segment simply requires a cross-visit AND of all segment filters. Making use of simpler evaluations on much smaller sets of data can be an effective approach to data analytics at a large scale

Stateful metadata for big data

Large volumes of data, characterized by large variety and high update velocities, pose challenges in terms of storage, application of concurrently occurring frequent updates, and serving processes that require the most accurate version of the data simultaneously. In most current schemes, it is not possible to guarantee all of these characteristics and a relaxing one or more requirements is necessary. The present disclosure describes a scalable, easy-to-maintain metadata mechanism that is fast and efficient to update, and can provide all the above guarantees on data. The metadata maintains lightweight validity markers, and simple algebra is performed thereof to surface the most up to date and accurate data while enabling constant updates to the data in a non-blocking fashion

Application Specific Datapath Extension with Distributed I/O Functional Units

Abstract — Performance of an application can be improved through augmenting the processor with Application specific Functional Units (AFUs). Usually a cluster of operations identified from the application forms the behavior of an AFU. Several researchers studied the impact of Input and Output (I/O) constraints for a legal operation cluster on the overall achievable speedup. The general observation is that the speedup potential grows with the relaxation of I/O constraints. Going further, in this paper, we investigate the speedup potential of AFUs in the absence of I/O constraints. Design challenge in the absence of I/O constraints is addressed in a very practical manner, through the identification of maximal convex subgraphs. Usually the available register ports are few but the number of inputs/outputs of the identified patterns are likely to be large. We solve the register port limitation by the design of distributed I/O functional units, in which the operands are communicated in multiple cycles. The experimental results show that selection of maximal clusters achieves average 50 % higher speedup than selecting I/O constrained operation clusters. Also, our identification algorithm runs 2 to 3 orders faster than an exhaustive identification approach. I

A High-Level Synthesis Flow for Custom Instruction Set Extensions for Application-Specific Processors

Custom instruction set extensions (ISEs) are added to an extensible base processor to provide application-specific functionality at a low cost. As only one ISE executes at a time, resources can be shared. This paper presents a new high-level synthesis flow targeting ISEs. We emphasize a new technique for resource allocation, binding, and port assignment during synthesis. Our method is derived from prior work on datapath merging, and increases area reduction by accounting for the cost of multiplexors that must be inserted into the resulting datapath to achieve multi-operational functionality