Cost-aware design and simulation of electrical energy systems

One fundamental dimension in the design of an electrical energy system (EES) is the economic analysis of the possible design alternatives, in order to ensure not just the maximization of the energy output but also the return on the investment and the possible profits. Since the energy output and the economic figures of merit are intertwined, for an accurate analysis it is necessary to analyze these two aspects of the problem concurrently, in order to define effective energy management policies. This paper achieves that objective by tracking and measuring the energy efficiency and the cost effectiveness in a single modular framework. The two aspects are modeled separately, through the definition of dedicated simulation layers governed by dedicated virtual buses that elaborate and manage the information and energy flows. Both layers are simulated concurrently within the same simulation infrastructure based on SystemC-AMS, so as to recreate at runtime the mutual influence of the two aspects, while allowing the use of different discrete time scales for the two layers. Thanks to the tight coupling provided by the single simulation engine, our method enables a quick estimation of various cost metrics (net costs, annualized costs, and profits) of any configuration of EES under design, via an informed exploration of the alternatives. To prove the effectiveness of this approach, we apply the proposed strategy to two EES case studies, we explored various management strategies and the presence of different types and numbers of power sources and energy storage devices in the EES. The analysis proved to allow the identification of the optimal profitable solutions, thereby improving the standard design and simulation flow of EES

A Semi-Empirical Model of PV Modules Including Manufacturing I-V Mismatch

This paper presents an analysis of the impact of manufacturing variability in PV modules when interconnected into a large PV panel. The key enabling technology is a compact semiempirical model, that is built solely from information derived from datasheets, without requiring extraction of electrical parameters or measurements. The model explicits the dependency of output power on those quantities that are heavily affected by variability, like short circuit current and open circuit voltage. In this way, variability can be included with Monte Carlo techniques and tuned to the desired distributions and tolerance. In the experimental results, we prove the effectiveness of the model in the analysis of the optimal interconnection of PV modules, with the goal of reducing the impact of variability

Improving PPG-based Heart-Rate Monitoring with Synthetically Generated Data

Improving the quality of heart-rate monitoring is the basis for a full-time assessment of people’s daily care. Recent state-of-the-art heart-rate monitoring algorithms exploit PPG and inertial data to efficiently estimate subjects’ beats-per-minute (BPM) directly on wearable devices. Despite the easy-recording of these signals (e.g., through commercial smartwatches), which makes this approach appealing, new challenges are arising. The first problem is fitting these algorithms into low-power memory-constrained MCUs. Further, the PPG signal usually has a low signal-to-noise ratio due to the presence of motion artifacts (MAs) arising from movements of subjects’ arms. In this work, we propose using synthetically generated data to improve the accuracy of PPG-based heart-rate tracking using deep neural networks without increasing the algorithm’s complexity. Using the TEMPONet network as baseline, we show that the HR tracking Mean Absolute Error (MAE) can be reduced from 5.28 to 4.86 BPM on PPGDalia dataset. Noteworthy, to do so, we only increase the training time, keeping the inference step unchanged. Consequently, the new and more accurate network can still fit the small memory of the GAP8 MCU, occupying 429 KB when quantized to 8bits

A Cross-level Verification Methodology for Digital IPs Augmented with Embedded Timing Monitors

Smart systems implement the leading technology advances in the context of embedded devices. Current design methodologies are not suitable to deal with tightly interacting subsystems of different technological domains, namely analog, digital, discrete and power devices, MEMS and power sources. The interaction effects between the components and between the environment and the system must be modeled and simulated at system level to achieve high performance. Focusing on digital subsystem, additional design constraints have to be considered as a result of the integration of multi-domain subsystems in a single device. The main digital design challenges combined with those emerging from the heterogeneous nature of the whole system directly impact on performance, hence propagation delay, of the digital component. In this paper we propose a design approach to enhance the RTL model of a given digital component for the integration in smart systems, and a methodology to verify the added features at system-level. The design approach consists of ``augmenting'' the RTL model through the automatic insertion of delay sensors, which are capable of detecting and correcting timing failures. The verification methodology consists of an automatic flow of two steps. Firstly the augmented model is abstracted to system-level (i.e., SystemC TLM); secondly mutants, which are code mutations to emulate timing failures, are automatically injected into the abstracted model. Experimental results demonstrate the applicability of the proposed design and verification methodology and the effectiveness of the simulation performance

Addressing the Smart Systems Design Challenge: The SMAC Platform

This article presents the concepts, the organization, and the preliminary application results of SMAC, a smart systems co-design platform. The SMAC platform, which has been developed as Integrated Project (IP) of the 7th ICT Call under the Objective 3.2 \u201cSmart components and Smart Systems integration\u201d addresses the challenges of the integration of heterogeneous and conflicting domains that emerge in the design of smart systems. SMAC includes methodologies and EDA tools enabling multi-disciplinary and multi-scale modelling and design, simulation of multidomain systems, subsystems and components at different levels of abstraction, system integration and exploration for optimization of functional and non-functional metrics. The article presents the preliminary results obtained by adopting the SMAC platform for the design of a limb tracking smart system

Bioformers: Embedding Transformers for Ultra-Low Power sEMG-based Gesture Recognition

Human-machine interaction is gaining traction in rehabilitation tasks, such as controlling prosthetic hands or robotic arms. Gesture recognition exploiting surface electromyographic (sEMG) signals is one of the most promising approaches, given that sEMG signal acquisition is non-invasive and is directly related to muscle contraction. However, the analysis of these signals still presents many challenges since similar gestures result in similar muscle contractions. Thus the resulting signal shapes are almost identical, leading to low classification accuracy. To tackle this challenge, complex neural networks are employed, which require large memory footprints, consume relatively high energy and limit the maximum battery life of devices used for classification. This work addresses this problem with the introduction of the Bioformers. This new family of ultra-small attention-based architectures approaches state-of-the-art performance while reducing the number of parameters and operations of 4.9 ×. Additionally, by introducing a new inter-subjects pre-training, we improve the accuracy of our best Bioformer by 3.39 %, matching state-of-the-art accuracy without any additional inference cost. Deploying our best performing Bioformer on a Parallel, Ultra-Low Power (PULP) microcontroller unit (MCU), the GreenWaves GAP8, we achieve an inference latency and energy of 2.72 ms and 0.14 mJ, respectively, 8.0× lower than the previous state-of-the-art neural network, while occupying just 94.2 kB of memory

Combining Wire Swapping and Spacing for Low-Power Deep-Submicron Buses

We propose an approach for reducing the energy consumption of address buses that targets both the switching and the crosstalk components of power dissipation. The method is based on the combined application of two techniques. First, selective wire swapping is applied in such a way that bus wires with high coupling activity are kept far away from each other. Then, the slack available in the floorplanning for the routing of the bus wire is exploited to realize a bus with non-uniform inter-wire spacing. Both swapping and placement are driven by the switching data obtained from the analysis of typical address bus traces, and can be successfully applied to any address bus. Results on a set of profiled address streams show the effectiveness of the proposed approach

Energy-Efficient Bus Encoding for LCD Digital Display Interfaces

This paper presents a low-power encoding technique explicitly devised for the digital interface to Liquid Crystal Displays (LCDs). The proposed code, called Limited Intra-Word Transition (LIWT), exploits the existing inter-pixel correlation of typical images, by selectively transmitting a suitably encoded representation of the difference between adjacent pixels. Since all LCD transmission protocols are serial, the LIWT code specifically targets the reduction of intra-word transitions by defining codewords with limited intraword transition counts. Three are the main improvements of the proposed code with respect to previous solutions. First, it provides superior energy savings at a reduced complexity; second, it can adapt to the different signaling schemes of standard protocols; third, it can account for DC-balancing without requiring additional logic to implement it. The application of the encoding to a series of standard images resulted in transition savings over 60% on average with respect to the TMDS, LVDS and GVIF protocols. A DC-balanced version of the encoding achieves almost perfect balancing, with only a 2% reduction of the transition savings

A Low-Power Encoding Scheme for GigaByte Video Interfaces

This works presents a low-power encoding techniques suitable for digital interface of Liquid Crystal Displays (LCD), an in particular for a standard interface called Gigabyte Video Interface (GVIF), which is employed in many laptop computers. The encoding is based on the spatial correlation that exists between consecutive pixels and, exploiting the serial nature of the transmission protocol, it encodes pixel differences with limited intra-word transition codewords so that to minimize the transition activity over serial links. Application of this idea to GVIF-encoded data shows average transition savings of about 50% with respect to plain GVIF data, with the addition of relatively simple encoding architecture