Modeling techniques suitable for CAD-based design of internal matching networks of high-power RF/microwave transistors

A scalable and accurate simulation technique to be used for the computer-aided design (CAD) of matching networks employed within high-power RF transistors is presented. A novel measurement methodology is developed and utilized during the validation of the proposed analysis approach. Appropriate segmentation techniques were developed, which are consistent with the design approach of the high-power transistor, that take into account the overall complexity of the internal match of most modern RF high-power transistors, while preserving important electromagnetic interactions. By being able to properly decouple the linear portion of the overall packaged transistor model, an objective accuracy assessment via the comparison of measured versus simulated results of the internal matching network was accomplished. The level of accuracy obtained provides credence to the idea of a full CAD-driven design process of the internal match of high-power RF transistors. © 2006 IEEE

Modeling and characterization of RF and microwave power fets

© Cambridge University Press 2007 and Cambridge University Press, 2009.This 2007 book is a comprehensive exposition of FET modeling, and is a must-have resource for seasoned professionals and new graduates in the RF and microwave power amplifier design and modeling community. In it, you will find descriptions of characterization and measurement techniques, analysis methods, and the simulator implementation, model verification and validation procedures that are needed to produce a transistor model that can be used with confidence by the circuit designer. Written by semiconductor industry professionals with many years' device modeling experience in LDMOS and III-V technologies, this was the first book to address the modeling requirements specific to high-power RF transistors. A technology-independent approach is described, addressing thermal effects, scaling issues, nonlinear modeling, and in-package matching networks. These are illustrated using the current market-leading high-power RF technology, LDMOS, as well as with III-V power devices

Modeling techniques suitable for CAD-based design of internal matching networks of high-power RF/microwave transistors

A scalable and accurate simulation technique to be used for the computer-aided design (CAD) of matching networks employed within high-power RF transistors is presented. A novel measurement methodology is developed and utilized during the validation of the proposed analysis approach. Appropriate segmentation techniques were developed, which are consistent with the design approach of the high-power transistor, that take into account the overall complexity of the internal match of most modern RF high-power transistors, while preserving important electromagnetic interactions. By being able to properly decouple the linear portion of the overall packaged transistor model, an objective accuracy assessment via the comparison of measured versus simulated results of the internal matching network was accomplished. The level of accuracy obtained provides credence to the idea of a full CAD-driven design process of the internal match of high-power RF transistors. © 2006 IEEE

Modeling and characterization of RF and microwave power fets

© Cambridge University Press 2007 and Cambridge University Press, 2009.This 2007 book is a comprehensive exposition of FET modeling, and is a must-have resource for seasoned professionals and new graduates in the RF and microwave power amplifier design and modeling community. In it, you will find descriptions of characterization and measurement techniques, analysis methods, and the simulator implementation, model verification and validation procedures that are needed to produce a transistor model that can be used with confidence by the circuit designer. Written by semiconductor industry professionals with many years' device modeling experience in LDMOS and III-V technologies, this was the first book to address the modeling requirements specific to high-power RF transistors. A technology-independent approach is described, addressing thermal effects, scaling issues, nonlinear modeling, and in-package matching networks. These are illustrated using the current market-leading high-power RF technology, LDMOS, as well as with III-V power devices

Increased feedback due to package mounting

The affect of the ground step discontinuity created by a difference in package and printed circuit board (PCB) thickness was studied. It is observed that the step in the reference conductor can be represented by a series inductance and its value depends on the height of the step and the width of the transmission line above it. The overall circuit affects for a packaged transistors were simulated with commercially available electromagnetic 2D and 3D CAD tools. The results show that the discontinuity creates an inductive feedback path around the package

On the development of CAD techniques suitable for the design of high-power RF transistors

A full-wave modeling procedure was developed to simulate the package, bonding wires, and MOS capacitors used in the design of matching networks found within RF/microwave power transistors. The complex packaging environment was segmented into its constituent components and simulation techniques were developed for each component, as well as the inter-element coupling. An S-parameter test fixture and package was developed that permits measurements of these types of devices. The simulation and measurement procedures were used to model various circuits. Measured S-parameters and those obtained using the full-wave methodology were in good agreement. Simulation results using an inductance-only bonding-wire model were performed and differences between the S-parameters were observed. A detailed examination of the loss introduced by the matching network was performed and simulations and measurements matched closely. © 2005 IEEE

Increased feedback due to package mounting

The affect of the ground step discontinuity created by a difference in package and printed circuit board (PCB) thickness was studied. It is observed that the step in the reference conductor can be represented by a series inductance and its value depends on the height of the step and the width of the transmission line above it. The overall circuit affects for a packaged transistors were simulated with commercially available electromagnetic 2D and 3D CAD tools. The results show that the discontinuity creates an inductive feedback path around the package