Generalized Symmetrical 3 dB Power Dividers with Complex Termination Impedances

The paper introduces a class of two-way, 3 dB narrowband power dividers (combiners), closed on complex termination impedances, that generalizes a number of topologies presented during past years as extensions of the traditional Wilkinson design. Adopting even-odd mode analysis, we demonstrate that, under very broad assumptions, any axially symmetric reactive 3-port can be designed to operate as a 3 dB two-way power divider, by connecting a properly designed isolation impedance across two symmetrically but arbitrarily located additional ports. We show that this isolation element can be evaluated by a single input impedance or admittance CAD simulation or measurement; moreover, an explicit expression is given for the isolation impedance. The theory is shown to lead to the same design as for already presented generalizations of the Wilkinson divider; further validation is provided through both simulated and experimental case studies, and an application of the theory to the design of broadband or multi-band couplers is suggested

Efficiency versus linearity trade-off in an S-band class-AB power amplifier

This paper presents a design strategy to simultaneously optimize the efficiency and linearity of a single-device class-AB power amplifier, given minimum output power and gain requirements. The adopted linearity metric is the highest inter-modulation distortion in a two-tone test with 20MHz spacing. The simultaneous selection of optimum source and load terminations that provide the best trade-off among all of the requirements is described in detail, and the synthesis of the matching networks is then presented. A prototype is developed based on a 6W packaged GaN device around 3.5 GHz, manufactured and measured. According to the measured results, the amplifier achieves output power higher than 38dBm with associated gain higher than 12 dB and saturated power-added efficiency in excess of 73% in a single-tone test at 3.25 GHz, while providing a 33% power-added efficiency and -30 dBc inter-modulation distortion in the 20MHz two-tone test

Continuous Inverse Class-F GaN Power Amplifier with 70% Efficiency over 1.4-2 GHz Bandwidth

This work presents the design and experimental characterization of a wideband continuous inverse class-F power amplifier, covering several bands in the 5G FR1 frequency range, and thus suitable for base station applications. The design spaces of the class-F and inverse class-F in terms of input and output terminations are reviewed and compared, and the design choices relative to an implementation using a packaged device are described. Measurements show a saturated output power of 40 dBm, with corresponding efficiency and gain higher than 70% and 13 dB, respectively, over 1.4-2 GHz. The performance is well in line with the state of the art and is accurately predicted by simulations, proving the effectiveness of the design strategy

Compact GaN-based Stacked Cells for 5G Applications at 26 GHz

This work presents the development of two 2-FET stacked cells at 26 GHz in the WIN Semiconductors 150 nm power GaN/SiC technology. Two different compact layouts, based on the same circuit scheme, are designed targeting similar performance in the FR2 5G frequency band. One version favoring distance between components, to relieve electromagnetic cross-talk, and the other favoring instead symmetry. The cells have been conceived as basic building blocks for the development of high-power 5G amplifiers, rather than as stand-alone amplifiers, hence including only input matching and stabilization networks. Based on large-signal simulations on the optimum load, the cells are expected to deliver around 34 dBm with an efficiency higher than 35% at 26 GHz, and a linear gain of 10 dB. The output power performance is maintained from 24.5 GHz to 27.5 GHz, where the saturated efficiency is above 30 % for both cells. The small-signal experimental characterization results are in very good agreement with the simulations, proving the effectiveness of the electromagnetic simulation setup adopted for all the passive structures, despite the challenges posed by the compact layouts

Low-Bias-Complexity Ku-band GaN MMIC Doherty Power Amplifier

This paper present a two-stage Doherty power amplifier designed to maximize the efficiency at 6 dB back-off while minimizing the complexity in terms of bias voltages. The amplifier has been manufactured on a GaN-SiC 150 nm monolithic microwave integrated circuit technology. The fabricated chip, measured in continuous wave conditions, maintains a linear gain higher than 13 dB, a saturated output power in excess of 34 dBm, with a power-added efficiency higher than 20% both at saturation and at 6 dB output back-off, over the 14.5 GHz-17.25 GHz band, favorably comparing with the present state of the art for similar applications

Optimisation of a Doherty power amplifier based on dual-input characterisation

The success of the Doherty architecture compared to other efficiency enhancement techniques derives mainly from its simple design and full-RF nature, not requiring complex digital signal processing to achieve high back-off efficiency. In this work we propose a design strategy for the optimisation of a Doherty power amplifier to mitigate the typical practical issues of this architecture related to inaccuracy of the non-linear model and of the manufacturing. The approach is based on the experimental characterisation of a dual-input Doherty prototype without input section. This test structure is obtained from a single-input Doherty amplifier, designed only through non-linear simulations, by removing the input section and allowing for separate control of the two RF inputs. From the collected data, approximated functions for the phase shift and power splitting versus frequency are identified to be realizable in hardware with RF networks. Compared to the reference single-input Doherty stage, a significantly improved behavior is registered in terms of output power (up to 2.7 dB), efficiency at saturation and back-off (30 % and 15 % respectively) and power gain (2 dB)

A Simple Method to Identify Parametric Oscillations in Power Amplifiers Using Harmonic Balance Solvers

A qualitative method to verify the presence of parametric oscillations at f_0/2 in power amplifiers (PAs) is presented and validated. It relies on the simultaneous application of fundamental and subharmonic tones to trigger possible parametric oscillations and can be implemented in any commercial harmonic balance solver without requiring any external software that may be expensive or however not available to the designer. Wide applicability is guaranteed by the fact that this method does not require access to any internal node of the circuit. In fact, the amplifier is handled as a black-box where only the input and output ports are accessible. The stability check is first demonstrated on a simplified case study and then validated on a real K-band integrated PA, where it correctly reproduces with simulations the parametric oscillations observed by measurements. On the redesigned amplifier, the proposed test predicted the absence of oscillations, which has been confirmed by the experimental characterization

Design of a wideband doherty power amplifier with high efficiency for 5g application

This paper discusses the design of a wideband class AB-C Doherty power amplifier suitable for 5G applications. Theoretical analysis of the output matching network is presented, focusing on the impact of the non-ideally infinite output impedance of the auxiliary amplifier in back off, due to the device’s parasitic elements. By properly accounting for this effect, the designed output matching network was able to follow the desired impedance trajectories across the 2.8 GHz to 3.6 GHz range (fractional bandwidth = 25%), with a good trade-off between efficiency and bandwidth. The Doherty power amplifier was designed with two 10 W packaged GaN HEMTs. The measurement results showed that it provided 43 dBm to 44.2 dBm saturated output power and 8 dB to 13.5 dB linear power gain over the entire band. The achieved drain efficiency was between 62% and 76.5% at saturation and between 44% and 56% at 6 dB of output power back-off

A Novel Stacked Cell Layout for High Frequency Power Applications

This letter presents an innovative stacked cell, where the common source device is split in two smaller devices leading to a more compact and symmetric structure, with almost negligible parasitics associated to the transistors connection. This novel configuration is rigorously compared, for the first time, with the two classical approaches commonly adopted to physically connect the two devices. The three different layouts are fabricated in Gallium Nitride technology for high frequency power applications, and experimentally compared by means of an extensive measurement campaign performed on several loads and in different bias conditions, ranging from class AB to C. The proposed novel configuration outperforms the other two in all conditions, thanks to the advantages of adopting two smaller devices with reduced parasitics, higher gain and higher power density. These features are common to different technologies, thus making the novel topology widely applicable for the design of high frequency stacked cells

Evaluation of a stacked-FET cell for high-frequency applications

This paper presents the design, electromagnetic simulation strategies and experimental characterisation of a two-stage stacked-FET cell in a 100 nm GaN on Si technology around 18.8 GHz, suited for Ka band satellite downlink applications. A good agreement is found between the electromagnetic simulations and the measured performance on the manufactured prototype, thus demonstrating that a successful voltage combining architecture can be obtained in the frequency range of interest with the selected topology, based on a symmetric fork-like connection between the transistors. This proves the effectiveness of an appropriate electromagnetic simulation set-up in correctly predicting the crosstalk, which typically affects this structure, leading to a correct stacking operation