45 research outputs found

    A performance-driven micro-cell compiler for CMOS sea-of-gates arrays

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    A performance analysis tool for performance-driven micro-cell generation

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    A new method is presented to determine the power dissipation and propagation-delay time of small logical blocks (micro-cells). This method is a combination of the RC-tree and the macro modeling methods. It is a fast and accurate method, three orders of magnitude faster that SPICE, while the maximal error is ten percent. This method can be used in a performance-driven micro-cell generator for a sea-of-gates environmen

    The Petrol Approach to High-Level Power Estimation

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    High-level power estimation is essential for designing complex low-power ICs. However, the lack of flexibility, or restriction to synthesizable code of previously presented high-level power estimation approaches limits their use. In this paper we present a novel, more general and flexible high-level power estimation approach, that avoids these limitations. Petrol, as we call it, is not limited to specialized application domains, synthesizable VHDL, or data path parts of a design. We show that glitches can be usefully modeled at higher levels of abstraction. The Petrol approach shows good correlation with gate-level power estimates. It is currently used for commercial designs. 1 Introduction The huge integration capability of modern technologies (several millions of transistors) allows very complex systems on a single IC, such as MPEG2 encoders and digital audio channel decoders. For these systems power dissipation is a critical issue, since it is often the bottleneck for further inte..
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