Deterministic Cache-based Execution of On-line Self-Test Routines in Multi-core Automotive System-on-Chips

Traditionally, the usage of caches and deterministic execution of on-line self-test procedures have been considered two mutually exclusive concepts. At the same time, software executed in a multi-core context suffers of a limited timing predictability due to the higher system bus contention. When dealing with selftest procedures, this higher contention might lead to a fluctuating fault coverage or even the failure of some test programs. This paper presents a cache-based strategy for achieving both deterministic behaviour and stable fault coverage from the execution of self-test procedures in multi-core systems. The proposed strategy is applied to two representative modules negatively affected by a multi-core execution: synchronous imprecise interrupts logic and pipeline hazard detection unit. The experiments illustrate that it is possible to achieve a stable execution while also improving the state-of-the-art approaches for the on-line testing of embedded microprocessors. The effectiveness of the methodology was assessed on all the three cores of a multi-core industrial System- on-Chip intended for automotive ASIL D applications

Increasing the Robustness of Software Test Libraries in Multi-core System-on-Chips

Electronic Control Units based on a multi-core architecture are commonly found in the automotive domain. For increasing the reliability of such systems, the ISO 26262 functional safety standard mandates different safety mechanisms. Among these, Software Test Libraries (STLs) are increasingly becoming adopted for the on-line testing of the processor cores. Some of the test procedures composing the STL require the execution of an exact instructions stream. While for a single-core scenario these constraints can be easily achieved, the embedded software executed in multi-core context suffers of a limited determinism due to the higher system bus contention. In this scenario, some test programs requiring a deterministic execution might fail when executed in field, since the test program signature is influenced by the whole system activity. The paper presents a cache-based strategy for increasing the robustness of self-test procedures that become unreliable in a multi-core execution. Such strategy guarantees a stable in-field execution, while it does not impact the test program memory requirements. The proposed method was evaluated on a multi-core industrial System-on-Chip manufactured by STMicroelectronics intended for automotive ASIL D applications