A Demonstrator Programme For The Atlas Level-1 Calorimeter Trigger

This document describes work to demonstrate the feasibility of the level-1 trigger design presented in the ATLAS Technical Proposal. In the phase-I programme already completed, a prototype custom integrated circuit to carry out the e.m. cluster-finding algorithm was produced and tested, and work was done on bunchcrossing identification. In 1995 further studies will be made of bunch-crossing identification, using a new module in conjunction with the phase-I trigger. The phase-II system, scheduled for 1996, will concentrate on the issues of high-speed optical and electrical data transmission, and signal fanout on transmission-line backplanes. Contents 1 Overview .............................................................................................................. 2 2 Phase-I demonstrator programme ........................................................................ 2 2.1 Trigger algorithm ..................................................................................... ..

The level-1 calorimeter trigger system for ATLAS

We describe the design of a digital calorimeter trigger processor system which could form a major part of the ATLAS level-1 trigger system. Utilising novel techniques, but with today’s technologies, the system can be contained within six electronics crates and will provide the central trigger logic with signals from events with high-pT electrons, photons, jets and missing ET. Communication with the trigger digitisation system will employ commercial high-speed optical links, terminating in multi-chip modules (MCMs) incorporating custom-designed integrated optics. Simulation studies combined with an extensive demonstrator programme have been used to develop flexible digital algorithms with programmable parameters for bunch-crossing identification and electromagnetic cluster-finding. These algorithms will be embedded in semi-custom application-specific integrated circuits, of which five types will be designed. Inter-crate data fan-out will be achieved by means of optical splitters, while communication within crates will use transmission-line backplanes. The remaining technical issues will be studied in the final phase of the current R&D demonstrator programme. A parallel demonstrator programme is also under way to study alternative techniques with the potential for future system enhancement