Near-unity quantum yields from chloride treated CdTe colloidal quantum dots

Colloidal quantum dots (CQDs) are promising materials for novel light sources and solar energy conversion. However, trap states associated with the CQD surface can produce non‐radiative charge recombination that significantly reduces device performance. Here a facile post‐synthetic treatment of CdTe CQDs is demonstrated that uses chloride ions to achieve near‐complete suppression of surface trapping, resulting in an increase of photoluminescence (PL) quantum yield (QY) from ca. 5% to up to 97.2 ± 2.5%. The effect of the treatment is characterised by absorption and PL spectroscopy, PL decay, scanning transmission electron microscopy, X‐ray diffraction and X‐ray photoelectron spectroscopy. This process also dramatically improves the air‐stability of the CQDs: before treatment the PL is largely quenched after 1 hour of air‐exposure, whilst the treated samples showed a PL QY of nearly 50% after more than 12 hours

Double-polysilicon self-aligned lateral bipolar transistors

A new lateral bipolar junction transistor that utilises a double-polysilicon self-aligned structure to maximise high-frequency performance is introduced. Silicon-on-oxide (SOI) wafers are used to isolate devices from the substrate and to minimise parasitic substrate capacitances(CJCS0) around 1.3–2.6 fF (substrate is ground). A SOI thickness of 0.2–0.5 μm combined with 0.13–0.25 μm lithography could allow a reduction of transistor dimensions down to (0.2–0.5) · (0.13–0.25) lm2 and give an estimated minimum emitter/base junction capacitance(CJE0) of 0.54–1.36 fF. Simple device isolation is predicted to produce a small collector/base junction capacitance (CJC0) of 0.42–2.00 fF. Furthermore, use of a double base contact can help reduce base resistance (RB) to 0.43–1.17 kW and a wide collector window directly contacted to the collector is estimated to result in around 0.66–1.58 kW collector resistance (RC). By taking all parameters into account a cut-off frequency (fT) of 69–116 GHz and maximum oscillation frequency (fmax) of 61–128 GHz is predicted for this design, in addition a gain of 47–101(using minimum gain enhancement) and roughly 10.6–21.0 ps ECL propagation delay time, at a current of 0.4–1.0 mA could be achieved. Our simulations indicate that this new doubled-polysilicon self-aligned structure could outperform all other silicon bipolar transistors that have been reported

Lateral SiGe heterojunction bipolar transistor by confined selective epitaxial growth: simulation and material growth

A new design for a lateral SiGe HBT has been based on development studies of confined lateral selective epitaxial growth in cavities built into silicon-on-insulator wafers. A design process is described and modelled. Device simulations indicate devices with maximum fT of 22 GHz with peak gain of 95 and fmax of 14 GHz can be obtained by the processes outlined. The simulation results highlight the feasibility of the design and further improvements and scaling of the device would allow the transistor to operate at even higher frequencies and lower power