LHC1: a semiconductor pixel detector readout chip with internal, tunable delay providing a binary pattern of selected events

The Omega3/LHCl pixel detector readout chip comprises a matrix of 128 X 16 readout cells of 50 mu m X 500 mu m and peripheral functions with 4 distinct modes of initialization and operation, together more than 800 000 transistors. Each cell contains a complete chain of amplifier, discriminator with adjustable threshold and fast-OR output, a globally adjustable delay with local fine-tuning, coincidence logic and memory. Every cell can be individually addressed for electrical test and masking, First results have been obtained from electrical tests of a chip without detector as well as from source measurements, The electronic noise without detector is similar to 100 e(-) rms. The lowest threshold setting is close to 2000 e(-) and non-uniformity has been measured to be better than 450 e(-) rms at 5000 e(-) threshold. A timewalk of < 10 ns and a precision of < 6 ns rms on a delay of 2 mu s have been measured. The results may be improved by further optimization

On the performance and limitations of a dual threshold discriminator pixel readout circuit for LHC

The analog frontend of pixel readout electronics with dual threshold discriminator scheme has been measured extensively to determine the conditions for optimum performance as well as the circuits performance limitations. The $9 preamplifier shows a peaking time of 20 ns without capacitive load, which degrades to only 30 ns with a load of 350 fE The LEVEL-discriminator has an adjustable threshold in the range of 2000 to 6000 e/sup -/ with a variable$9 separation to the TIME-discriminator threshold of 800 to 1600e/sup -/. The circuit allows the full suppression of out-of-time signals under the conditions of 350 fF capacitive load and a total power consumption of 40 mu W per cell. $9 The untuned threshold dispersion is measured to be 320 e/sup -/ r.m.s., which reduces to 70 e/sup -/ r.m.s, after threshold adjust. The overall noise of the circuit reaches a value of about 200 e/sup -/ r.m.s. With 350 fF capacitive$9 load and 20 nA of parallel current at the preamplifier input. Further measurements characterize the time-over-threshold (TOT) behaviour and the double- pulse resolution of the circuit. (4 refs)

Dead-time free pixel readout architecture for ATLAS front-end IC

A low power sparse scan readout architecture has been developed for the ATLAS pixel front-end IC. The architecture supports a dual discriminator and extracts the time over threshold (TOT) information along with a 2-D spatial address $9 of the hits associating them with a unique 7-bit beam crossing number. The IC implements level-1 trigger filtering along with event building (grouping together all hits in a beam crossing) in the end of column (EOC) buffer. The$9 events are transmitted over a 40 MHz serial data link with the protocol supporting buffer overflow handling by appending error flags to events. This mixed-mode full custom IC is implemented in 0.8 mu HP process to meet the $9 requirements for the pixel readout in the ATLAS inner detector. The circuits have been tested and the IC provides dead-time-less ambiguity free readout at 40 MHz data rate

Frequency Synthesis for a Low-Power 2.4 GHz Receiver Using a BAW Oscillator and a Relaxation Oscillator

In this paper, a solution to realize local oscillators (LO) for a low power super-heterodyne receiver is presented. The first oscillator uses a bulk acoustic wave (BAW) resonator with high Q-factor. A quasi- harmonic quadrature relaxation oscillator with large tuning range is used to compensate for variations in the first oscillator and to cover the entire bandwidth for multiple channel selection

A Narrowband Multi-Channel 2.4 GHz MEMS-Based Transceiver

This paper presents a new radio architecture targeting RF transceivers for WSN, WBAN, and biomedical applications. The high miniaturization required by such applications is achieved thanks to the combination of high-Q MEMS devices, such as RF BAW resonators and filters and low frequency silicon resonators, together with a low-power RF IC. This requires a dedicated radio architecture accounting for the advantages and limitations of the MEMS devices. The paper presents such an architecture together with the design of some ultra-low-power and MEMS-specific circuits. The new radio is validated by the demonstration of RX and TX functionalities. The synthesizer, based on a low phase noise BAW DCO and a variable IF LO obtained by fractional division from the RF carrier, achieves a phase noise of - 113 dBc/Hz at 3 MHz. It can intermittently be locked to a low frequency reference (e.g. 32 kHz XTAL or thermally compensated silicon resonator) to correct for the BAW aging and thermal drift thanks to an ADPLL where the lock state can be memorized for nearly immediate settling after returning from an idle period. A sensitivity of - 87 dBm is obtained in receive at 100 kbps for a global power consumption of 6 mA. The transmitter demonstrates a high data rate quasi-direct 1-point modulation capability with the generation of a -4 dBm, 1 Mbps, GFSK signal with an overall current of 20 mA