2 research outputs found

    A 1.5mA, 2.4GHz ZigBee/BLE QLMVF Receiver Frond End with Split TCAs in 180nm CMOS

    No full text
    A low noise amplifier (LNA), mixer, quadrature voltage controlled oscillator (QVCO) and low pass filter (LPF) (overall called as QLMVF Cell) in two active stages for 2.4GHz ZigBee and Bluetooth low energy (BLE) direct conversion receiver is designed and presented. To achieve low power, QVCO, LNA and split trans-conductance amplifier (TCA)s are sharing bias current in the first stage. Similarly, trans impedance amplifier (TIA) and 3rd order LPF sharing the second stage bias current. The use of split TCAs avoiding I/Q cross talk even with 50% local oscillator (LO) signal and a current driven passive mixer down converting single ended RF signal into differential base band signal without the use of RF balun. The programmable LPF enables the receiver to operate in both ZigBee and BLE modes. Optimum input matching is achieved independent of bond wire effects by the use of varactor in the LNA. The design includes gain variation to achieve linearity requirements. The UMC 180nm CMOS extracted results of the QLMVF cell show, 42.5dB of conversion gain, 10dB of noise figure, less than-15dB of S11, 23dBm of 1dB compression, -8.5dBm of out band IIP3 and 57.6dB of spurious free dynamic range (SFDR). The proposed receiver front end consuming 2.7mW from 1.8V VDD and occupies an area of 1.5mm2

    0.8 V 450 μW 2.4 GHz PLL using back-gate QVCO for ZigBee/BLE standard in 0.18 μm CMOS

    No full text
    This paper proposes a PLL architecture targeting ZigBee (ZB) and Bluetooth LE (BLE) band. It employs a single well, direct back-gated Quadrature Voltage Controlled Oscillator (QVCO). An efficient, Integer-N, Multi Modulus Divider (MMD) using True Single Phase Clock (TSPC) logic is incorporated in the design to minimize the overall PLL power consumption. The QVCO gives phase noise of-110 dBc/Hz at 1 MHz offset. PLL consumes 450 mu W of power at 0.8 V supply with a settling time less than 25 mu s and core area is 705 mu m x 510 mu m at UMC 0.18 pm CMOS Mixed Mode Technology. PLL is successfully tested with the energy harvesting circuit
    corecore