Reducing load latency through memory instruction characterization.

Processor performance is directly impacted by the latency of the memory system. As processor core cycle times decrease, the disparity between the latency of an arithmetic instruction and the average latency of a load instruction will continue to increase. A wide-issue superscalar machine requires a memory system highly optimized for latency. This dissertation analyzes the patterns of data sharing between memory instructions and the address calculation chains leading up to each load instruction. The analysis of memory instruction data sharing patterns shows that the dynamic address stream can be broken into several independent streams. This observation is used to segment the first level of the memory hierarchy, including the memory disambiguation logic, into several independent partitions. A partitioned cache with eight partitions can be accessed in half the time of an equivalently-sized unpartitioned cache. An aggressive processor implementing a partitioned first-level cache outperformed the same processor implementing an equivalently-sized conventional cache by 4.5% on the SPECint00 benchmark suite. The analysis of address calculation chains demonstrates that, a relatively small number of unique functions are used in the calculation of memory data addresses within an application. A method of dynamically identifying these functions and reproducing them in hardware is developed. This technique allows the results of complex address calculations to be generated independently of the program instruction stream and without executing the instructions involved in the calculation. A processor utilizing this scheme outperformed a processor implementing conventional address prediction by 5.5% on the SPECint00 bench-mark suite.Ph.D.Applied SciencesElectrical engineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/123938/2/3106150.pd

Reducing the Performance Impact of Instruction Cache Misses by Writing Instructions into the Reservation Stations Out-of-Order

In conventional processors, each instruction cache fetch brings in a group of instructions. Upon encountering an instruction cache miss, the processor will wait until the instruction cache miss is serviced before continuing to fetch any new instructions. This paper presents a new technique, called out-oforder issue, which allows the processor to temporarily ignore the instructions associated with the instruction cache miss. The processor attempts to fetch the instructions that follow the group of instructions associated with the miss. These instructions are then decoded and written into the processor's reservation stations. Later, after the instruction cache miss has been serviced, the instructions associated with the miss are decoded and written into the reservation stations. (We use the term issue to indicate the act of writing instructions into the reservation stations. With this technique, instructions are not written into the reservation stations in program order. Hence, the term..

The biopax community standard for pathway data sharing

BioPAX (Biological Pathway Exchange) is a standard language to represent biological pathways at the molecular and cellular level. Its major use is to facilitate the exchange of pathway data (http://www.biopax.org). Pathway data captures our understanding of biological processes, but its rapid growth necessitates development of databases and computational tools to aid interpretation. However, the current fragmentation of pathway information across many databases with incompatible formats presents barriers to its effective use. BioPAX solves this problem by making pathway data substantially easier to collect, index, interpret and share. BioPAX can represent metabolic and signaling pathways, molecular and genetic interactions and gene regulation networks. BioPAX was created through a community process. Through BioPAX, millions of interactions organized into thousands of pathways across many organisms, from a growing number of sources, are available. Thus, large amounts of pathway data are available in a computable form to support visualization, analysis and biological discovery