Fault tolerance in VLSI.

A primary goal in microelectronic systems progress is the achievement of yet higher levels of functional integration. Today this is being addressed from two different perspectives: Firstly, introducing more circuitry onto the chips themselves and; secondly, packaging the chips in higher performance media. 'Wafer-Scale Integration (\MSI), whereby the chip assumes the size of a wafer, is one goal that combines elements from both of these perspectives. A purely advanced packaging approach is Hybrid Wafer-Scale Integration (HWSI), or silicon on silicon thin film hybrids, Both of these approaches offer many potential advantages, in terms of speed, reliability, power consumption, packaging density and cost. The potential advantages, as well as the disadvantages, are discussed in detail before a review of current WSI and HWSI projects is presented. Currently one factor that limits chip size growth are the defects incurred in the production of any integrated circuit. Defect tolerance provides the means to overcome this limitation and is particularly important for the achievement of WSI. A critical point in evaluating approaches to defect tolerance for VLSI, WSI and Ultra Large Scale Integration (ULSI) is the yield model used. A correct yield model allows the type and amount of the optimal level of defect tolerance to be determined. A. yield model is presented here that takes account of both clustering and the influence of the reconfigurable interconnect. Two different approaches are presented which would be used for different modeling applications: yield, and expected number of connected processors. The latter form has a number of advantages. The model is applied to a VLSI signal processing chip, and to a generalized chip, to determine the kind of chip structures that can best benefit from defect tolerance. It is found that in order to benefit from defect tolerance regular structures covering more than 20% to 30% of the chip are required. The yield model is also applied in a consideration of granularity effects on wafer-scale arrays. As a result of this discussion on granularity a new metric is suggested for evaluating array element architectures. Using this model as a basis, a number of alternative approaches to WSI are presented and evaluated. After a review of existing approaches, during which a suitable classification system is introduced, a new approach, called the "frame" approach is introduced. The frame scheme is aimed at the WSI implementation of 2D arrays, containing reasonably large elements. The design and implementation of WSI and HWSI examples of the "frame" scheme are presented. Practical lessons learnt about implementing WSI and HWSI designs are also discussed. Finally a detailed comparison of different approaches to implementing 2D arrays in WSI is undertaken. The relative merits of the frame scheme are affirmed in this section. Examples are presented that demonstrate the relative advantages and disadvantages of the various approaches, indicating the important points to be considered when designing wafer scale arrays.Thesis (Ph.D.) -- University of Adelaide, Dept. of Electrical and Electronic Engineering, 198

Flexible low power probability density estimation unit for speech recognition

Abstract — This paper describes the hardware architecture for a flexible probability density estimation unit to be used in a Large Vocabulary Speech Recognition System, and targeted for mobile platforms. The speech recognition system is based on Hidden Markov Models and consists of two computationally intensive parts – the probability density estimation using gaussian distributions, and the viterbi decoding. The power hungry nature of these computations prevents porting the application successfully to mobile devices. We have designed a flexible probability estimation unit that is both power efficient and meets real time requirements while being flexible enough to handle emerging speech recognition techniques. The flexible nature of the design allows it to utilize emerging power and computation reduction techniques (at the algorithm level) to achieve up to an 80 % power reduction as compared to conventional designs. I

Novel Hardware Implementation for Fast Address Lookups

The major bottleneck in the performance of routers is the address lookup for determining the next hop address. The problem of determining the next hop is made more complicated by the fact that routers store variable length prefixes in the forwarding tables. This paper describes a new hardware algorithm that gives a fast and efficient solution for address lookups. As implemented in the forwarding engine of a network processor or router, an overhead of a small on-chip SRAM and some additional circuitry is required. Forwarding table search is performed only on this SRAM, and subsequently only one DRAM access is needed for output port assignment. In our implementation, the throughput of the forwarding engine implemented is limited by the random access time of the off-chip DRAM. This means that a lookup is performed every 64ns giving over 15 million lookups per second. The throughput can be made much higher by using multiple DRAMs. The amount of on-chip SRAM is quite small and around 40KB of SRAM memory is required for a routing table of over 40,000 entries