2 research outputs found
Memory-Immersed Collaborative Digitization for Area-Efficient Compute-in-Memory Deep Learning
This work discusses memory-immersed collaborative digitization among
compute-in-memory (CiM) arrays to minimize the area overheads of a conventional
analog-to-digital converter (ADC) for deep learning inference. Thereby, using
the proposed scheme, significantly more CiM arrays can be accommodated within
limited footprint designs to improve parallelism and minimize external memory
accesses. Under the digitization scheme, CiM arrays exploit their parasitic bit
lines to form a within-memory capacitive digital-to-analog converter (DAC) that
facilitates area-efficient successive approximation (SA) digitization. CiM
arrays collaborate where a proximal array digitizes the analog-domain
product-sums when an array computes the scalar product of input and weights. We
discuss various networking configurations among CiM arrays where Flash, SA, and
their hybrid digitization steps can be efficiently implemented using the
proposed memory-immersed scheme. The results are demonstrated using a 65 nm
CMOS test chip. Compared to a 40 nm-node 5-bit SAR ADC, our 65 nm design
requires 25 less area and 1.4 less energy by
leveraging in-memory computing structures. Compared to a 40 nm-node 5-bit Flash
ADC, our design requires 51 less area and 13 less
energy
On-Sensor Data Filtering using Neuromorphic Computing for High Energy Physics Experiments
This work describes the investigation of neuromorphic computing-based spiking
neural network (SNN) models used to filter data from sensor electronics in high
energy physics experiments conducted at the High Luminosity Large Hadron
Collider. We present our approach for developing a compact neuromorphic model
that filters out the sensor data based on the particle's transverse momentum
with the goal of reducing the amount of data being sent to the downstream
electronics. The incoming charge waveforms are converted to streams of
binary-valued events, which are then processed by the SNN. We present our
insights on the various system design choices - from data encoding to optimal
hyperparameters of the training algorithm - for an accurate and compact SNN
optimized for hardware deployment. Our results show that an SNN trained with an
evolutionary algorithm and an optimized set of hyperparameters obtains a signal
efficiency of about 91% with nearly half as many parameters as a deep neural
network.Comment: Manuscript accepted at ICONS'2