Growth of High Quality Ge Layer on Silica Nano-Spheres Integrated Ge/Si Template Using UHV-CVD

We have investigated the growth of high quality Ge layer on Si substrate using silica nano-spheres (NSs), which behaved as masks to directly block threading dislocations. Two-step growth after the silica NS incorporation into the surface led to a coalesced Ge layer with low threading dislocation density (TDD). TDD in the resultant Ge layer was reduced from 6.4 × 10 8 to 6.9 × 10 7 cm −2 , and decreased further to 1.4 × 10 7 cm −2 by post annealing. In addition to the TDD reduction, we speculated that the suppression of {111} facet during the growth restricted significantly the generation of planar defects. © 2015 The Electrochemical Society. [DOI: 10.1149/2.0151503jss] All rights reserved. The growth of a high-quality Ge layer on Si has been a promising technology in relation to opto-electronic applications. A small bandgap of 0.67 eV at room temperature and a high absorption coefficient in the near-infrared region make Ge a strong candidate as a photodetector for use in optical communications. 1,2 When biaxial tensile stress is induced onto Ge, bandgap shrinkage occurs, transforming an indirect bandgap to a direct bandgap. 3 Tensile-strained Ge can easily be obtained by growing an epitaxial Ge layer on a Si substrate due to the difference in the thermal expansion coefficient between Si and Ge. A direct bandgap of tensile-strained Ge on Si improves the optical properties and demonstrates the possibility of the use of Ge as an emitter. 6,7 However, the lattice mismatch of 4.2% between Ge and Si makes it difficult to grow a high-quality Ge layer on a Si substrate due to the generation of threading dislocations (TDs) in the Ge layer with the density on the order of 10 8 -10 9 cm −2 . In order to utilize a Ge layer on a Si substrate for use in devices, the threading dislocation density (TDD) in the Ge layer should be reduced, as TDs degrade the performance of devices. There have been reports about TDD-reduced Ge growth using SiO 2 to terminate the TDs. In order to fabricate a Ge/Si template with silica NSs, an initial Ge layer of 550 nm was grown on a 6-inch Si(001) substrate using z E-mail: [email protected] ultrahigh vacuum chemical vapor deposition (UHV-CVD). The base pressure was 4 × 10 −9 torr, and GeH 4 was used as a precursor. Prior to the growth of the Ge, a 50-nm-thick Si buffer layer was grown at 550 • C. This was followed by the growth of a 40-nm-thick Ge buffer layer at 300 • C. Subsequently, the Ge layer was grown on top of the Ge buffer layer at 550 • C. During the growth, the working pressure was fixed at 17 mtorr. After the growth of the initial Ge layer, the surface of the Ge layer was etched for 1 min using a Secco etchant with the following composition: 2HF : 1K 2 Cr 2 O 7 (0.15 M), resulting in the selective etching of the defects on the surface. 14 Then, silica NSs were integrated into the etch pits by spin coating. Silica NS (50 nm in diameter) dispersed in ethanol was used, and the concentration was varied from 0.563 to 2.250 mg/ml. The RPM was set to 2000 and the coating time was 40 s. The Ge/Si template with silica NSs was then placed back into the UHV-CVD reactor. Before the regrowth of the Ge layer, the template was thermally cleaned at 650 • C for 30 min to remove the native oxide. 15 Then, Ge layers were grown at various temperatures ranging from 350 to 550 • C. Scanning electron microscopy (SEM) and atomic force microscopy (AFM) were used to investigate the surface morphologies of the Ge layers. The TDD was measured by counting the etch pits using the Secco etchant by SEM observation, and the defects were also examined by transmission electron microscopy (TEM). The defect-etched surface of the initial Ge layer is shown in 18-2

Multi-step plasma etching process for development of highly photosensitive InSb mid-IR FPAs

Reactive ion beam etching (RIBE) with CH4/H2/Ar or Cl2/Ar and ion beam etching (IBE) with Ar has been widely used for indium-contained compound semiconductors such as InAs, InP and InSb. To improve the performance of InSb FPAs, reduction of the ion-induced defects and the surface roughness is one of the key issues. To find the optimized plasma etching method for the fabrication of InSb devices, conventional plasma etching processes were comparatively investigated. RIBE of InSb was observed to generate residual by-products such as carbide and chloride causing the degradation of devices. On the other hand, very smooth surface was obtained by etching with N2. However, the etch rate of the N2 etching was too slow for the application to the device fabrication. As an alternative way to solve these problems, a multi-step plasma etching process, a combination of the Ar etching and the N2 etching, for InSb was developed. As gradually increasing the amount of N2 gas flow during the etching process, the plasma damage causing the surface roughen decreased and consequently smoother surface close to that of N2 RIE could be obtained. Furthermore, Raman analysis of the InSb surface after the plasma etching indicated clearly that the multi-step etching process was an effective approach in reducing the ion-induced damages on the surface. © 2014 SPIE.N

Multi-step plasma etching process for development of highly photosensitive InSb mid-IR FPAs

Reactive ion beam etching (RIBE) with CH4/H2/Ar or Cl2/Ar and ion beam etching (IBE) with Ar has been widely used for indium-contained compound semiconductors such as InAs, InP and InSb. To improve the performance of InSb FPAs, reduction of the ion-induced defects and the surface roughness is one of the key issues. To find the optimized plasma etching method for the fabrication of InSb devices, conventional plasma etching processes were comparatively investigated. RIBE of InSb was observed to generate residual by-products such as carbide and chloride causing the degradation of devices. On the other hand, very smooth surface was obtained by etching with N2. However, the etch rate of the N2 etching was too slow for the application to the device fabrication. As an alternative way to solve these problems, a multi-step plasma etching process, a combination of the Ar etching and the N2 etching, for InSb was developed. As gradually increasing the amount of N2 gas flow during the etching process, the plasma damage causing the surface roughen decreased and consequently smoother surface close to that of N2 RIE could be obtained. Furthermore, Raman analysis of the InSb surface after the plasma etching indicated clearly that the multi-step etching process was an effective approach in reducing the ion-induced damages on the surface. © 2014 SPIE.N

Analysis of failure of C-V characteristics of MIS structure with SiO2 passivation layer deposited on InSb substrate via Raman spectroscopy

The effect of interfacial phases on the electrical properties of Au/Ti/SiO2/InSb metal-insulator (oxide)-semiconductor (MIS or MOS) structures was investigated by capacitance-voltage (C-V) measurements. With increasing the deposition temperature of silicon oxide from 100 to 350°C using PECVD, the change in the interfacial phases between SiO2 and InSb were analyzed by resonant Raman spectroscopy to verify the relation between the breakdown of C-V characteristics and the change of interfacial phases. The shape of C-V characteristics was dramatically changed when the deposition temperature was above 300°C. The C-V measurements and Raman spectra represented that elemental Sb accumulation resulted from the chemical reaction of Sb oxide with InSb substrate was responsible for the failure in the C-V characteristics of MIS structure. Copyright © 2014 Materials Research Society.N

Highly efficient package configurations for white-light-emitting diode lamps

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Trapped whispering-gallery optical modes in white light-emitting diodes lamps with remote phosphor

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Investigation on Origin of efficiency droop in GaN-based high-power light-emitting diodes

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Analysis of high-power packages for white-light-emitting diode lamps with remote phosphor

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Improvements in light-extraction efficiency of light-emitting diodes with omni-directional reflectors

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