128 research outputs found
Successive Cancellation List Polar Decoder using Log-likelihood Ratios
Successive cancellation list (SCL) decoding algorithm is a powerful method
that can help polar codes achieve excellent error-correcting performance.
However, the current SCL algorithm and decoders are based on likelihood or
log-likelihood forms, which render high hardware complexity. In this paper, we
propose a log-likelihood-ratio (LLR)-based SCL (LLR-SCL) decoding algorithm,
which only needs half the computation and storage complexity than the
conventional one. Then, based on the proposed algorithm, we develop
low-complexity VLSI architectures for LLR-SCL decoders. Analysis results show
that the proposed LLR-SCL decoder achieves 50% reduction in hardware and 98%
improvement in hardware efficiency.Comment: accepted by 2014 Asilomar Conference on Signals, Systems, and
Computer
A Low-Latency FFT-IFFT Cascade Architecture
This paper addresses the design of a partly-parallel cascaded FFT-IFFT
architecture that does not require any intermediate buffer. Folding can be used
to design partly-parallel architectures for FFT and IFFT. While many cascaded
FFT-IFFT architectures can be designed using various folding sets for the FFT
and the IFFT, for a specified folded FFT architecture, there exists a unique
folding set to design the IFFT architecture that does not require an
intermediate buffer. Such a folding set is designed by processing the output of
the FFT as soon as possible (ASAP) in the folded IFFT. Elimination of the
intermediate buffer reduces latency and saves area. The proposed approach is
also extended to interleaved processing of multi-channel time-series. The
proposed FFT-IFFT cascade architecture saves about N/2 memory elements and N/4
clock cycles of latency compared to a design with identical folding sets. For
the 2-interleaved FFT-IFFT cascade, the memory and latency savings are,
respectively, N/2 units and N/2 clock cycles, compared to a design with
identical folding sets
A Gradient-Interleaved Scheduler for Energy-Efficient Backpropagation for Training Neural Networks
This paper addresses design of accelerators using systolic architectures for
training of neural networks using a novel gradient interleaving approach.
Training the neural network involves backpropagation of error and computation
of gradients with respect to the activation functions and weights. It is shown
that the gradient with respect to the activation function can be computed using
a weight-stationary systolic array while the gradient with respect to the
weights can be computed using an output-stationary systolic array. The novelty
of the proposed approach lies in interleaving the computations of these two
gradients to the same configurable systolic array. This results in reuse of the
variables from one computation to the other and eliminates unnecessary memory
accesses. The proposed approach leads to 1.4 - 2.2 times savings in terms of
number of cycles and savings in terms of memory accesses. Thus,
the proposed accelerator reduces latency and energy consumption.Comment: Proc. 2020 IEEE International Symposium on Circuits and Systems
(ISCAS
Systematic Design and Optimization of Quantum Circuits for Stabilizer Codes
Quantum computing is an emerging technology that has the potential to achieve
exponential speedups over their classical counterparts. To achieve quantum
advantage, quantum principles are being applied to fields such as
communications, information processing, and artificial intelligence. However,
quantum computers face a fundamental issue since quantum bits are extremely
noisy and prone to decoherence. Keeping qubits error free is one of the most
important steps towards reliable quantum computing. Different stabilizer codes
for quantum error correction have been proposed in past decades and several
methods have been proposed to import classical error correcting codes to the
quantum domain. However, formal approaches towards the design and optimization
of circuits for these quantum encoders and decoders have so far not been
proposed. In this paper, we propose a formal algorithm for systematic
construction of encoding circuits for general stabilizer codes. This algorithm
is used to design encoding and decoding circuits for an eight-qubit code. Next,
we propose a systematic method for the optimization of the encoder circuit thus
designed. Using the proposed method, we optimize the encoding circuit in terms
of the number of 2-qubit gates used. The proposed optimized eight-qubit encoder
uses 18 CNOT gates and 4 Hadamard gates, as compared to 14 single qubit gates,
33 2-qubit gates, and 6 CCNOT gates in a prior work. The encoder and decoder
circuits are verified using IBM Qiskit. We also present optimized encoder
circuits for Steane code and a 13-qubit code in terms of the number of gates
used.Comment: arXiv admin note: substantial text overlap with arXiv:2309.1179
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