Feedforward Architectures for parallel Viterbi Decoding

The Viterbi-Algorithm (VA) is a common application of dynamic programming. Since it contains a nonlinear feedback loop (ACS-feedback, ACS: add-compare-select), this loop is the bottleneck in high data rate implementations. In this paper we show that asymptotically the ACS-feedback no longer has to be processed recursively, i.e. there is no feedback, resulting in negligible performance loss. This can be exploited to derive purely feedforward architectures for Viterbi decoding, such that a modular cascadable implementation results. By designing one cascadable module, any speedup can be achieved simply by adding modules to the implementation. It is shown that optimization criteria, e.g. minimum latency or maximum hardware efficiency, are met by very different architectures. be seen that they merge into a unique path, the optimum one. The survivor depth D is then defined as that depth in which it is highly probable that all paths merge (time k-D). In a practical implementation of the VA, called Viterbi decoder (VD), this allows the decoded transition to be given out with latency D. The computation of the best path to each node of the trellis is achieved through dynamic programming by calculating a path metric yi,k for each state Si at every time instant k according to the "ACS-recursion" v s.: yi,k+l = ma.ximum (,\.. y,k + 'j,k) V j+i which for the simple example Fig. 1 leads to 1

Single-Cycle Implementations of Block Ciphers

Abstract. Security mechanisms to protect our systems and data from malicious adversaries have become essential. Strong encryption algo-rithms are an important building block of these solutions. However, each application has its own requirements and it is not always possible to find a cipher that meets them all. This work compares unrolled combina-torial hardware implementations of six lightweight block ciphers, along with an AES implementation as a baseline. Up until now, the majority of such ciphers were designed for area-constrained environments where speed is often not crucial, but recently the need for single-cycle, low-latency block ciphers with limited area requirements has arisen to build security architectures for embedded systems. Our comparison shows that some designers are already on this track, but a lot of work still remains to be done