Low disordered, stable, and shallow germanium quantum wells: a playground for spin and hybrid quantum technology

Buried-channel semiconductor heterostructures are an archetype material platform to fabricate gated semiconductor quantum devices. Sharp confinement potential is obtained by positioning the channel near the surface, however nearby surface states degrade the electrical properties of the starting material. In this paper we demonstrate a two-dimensional hole gas of high mobility ($5\times 10^{5}$ cm$^2$/Vs) in a very shallow strained germanium channel, which is located only 22 nm below the surface. This high mobility leads to mean free paths $\approx6 \mu m$, setting new benchmarks for holes in shallow FET devices. Carriers are confined in an undoped Ge/SiGe heterostructure with reduced background contamination, sharp interfaces, and high uniformity. The top-gate of a dopant-less field effect transistor controls the carrier density in the channel. The high mobility, along with a percolation density of $1.2\times 10^{11}\text{ cm}^{-2}$, light effective mass (0.09 m$_e$), and high g-factor (up to $7$) highlight the potential of undoped Ge/SiGe as a low-disorder material platform for hybrid quantum technologies

Reducing charge noise in quantum dots by using thin silicon quantum wells

Charge noise in the host semiconductor degrades the performance of spin-qubits and poses an obstacle to control large quantum processors. However, it is challenging to engineer the heterogeneous material stack of gate-defined quantum dots to improve charge noise systematically. Here, we address the semiconductor-dielectric interface and the buried quantum well of a $^{28}$Si/SiGe heterostructure and show the connection between charge noise, measured locally in quantum dots, and global disorder in the host semiconductor, measured with macroscopic Hall bars. In 5 nm thick $^{28}$Si quantum wells, we find that improvements in the scattering properties and uniformity of the two-dimensional electron gas over a 100 mm wafer correspond to a significant reduction in charge noise, with a minimum value of 0.29$\pm$0.02 $\mu$eV/sqrt(Hz) at 1 Hz averaged over several quantum dots. We extrapolate the measured charge noise to simulated dephasing times to cz-gate fidelities that improve nearly one order of magnitude. These results point to a clean and quiet crystalline environment for integrating long-lived and high-fidelity spin qubits into a larger system

Silicon/silicon-germanium heterostructures for spin-qubit quantum processors

Spin qubits in silicon have emerged as a promising candidate for a scalable quantum computer due to their small footprint, long coherence times, and their compatibility with advanced semiconductor manufacturing. However, all known spin qubit material hosts come with specific challenges, that limit the performance of quantum information processing. In this thesis we study Si/SiGe heterostructures, comprising a strained silicon (Si) quantum well which is sandwiched between two silicon-germanium (SiGe) barriers. Si/SiGe heterostructures designed to act as solid-state matrix to host spin qubits have three intrinsic material challenges that limit performance: hyperfine interaction, valley splitting, and charge noise. Therefore, to realize a scalable quantum computer in Si/SiGe heterostructures we first quantify the performance limiting parameters and subsequently, we improve them systematically with statistical significance. Acquiring data with statistical significance, however proves challenging for quantum devices in Si/SiGe heterostructures due to complicated and time-consuming fabrication schemes for device manufacturing, and the need of using dilution refrigerators that cool samples down to sub-Kelvin temperatures with only a limited amount of wires for electrical characterization of devices. Therefore, in this thesis we demonstrate fast growth-fabrication-measurement feedback cycles to accelerate our understanding on the materials and devices.We realize such fast feedback cycles by first establishing a unique workflow at TU Delft, allowing 100~mm wafer growth and fabrication. Subsequently in our first experiment, we overcome the wiring bottleneck by presenting a cryogenic multiplexing platform that multiplies DC wires inside of a dilution refrigerator. This cryogenic multiplexer platform uses commercially available CMOS components, is compatible with any dilution refrigerator, and allows us to measure thirteen chips in the same cooldown at a temperature of 50~mK and at magnetic fields of up to 10~T. We confirm these extreme measurement conditions by showing statistically significant quantum transport properties of industrially grown 300~mm $^{\text{nat}}$Si/SiGe wafers.In the following experimental chapters we then leverage the cryogenic multiplexer to successively tackle the performance limiting parameters of spin qubit processors in Si/SiGe heterostructures. In the second experiment we first analyze valley splitting in two dimensional electron gases and observe that valley splitting increases linearly with the electric field at the quantum Hall edge states of the device at a rate consistent with theoretical predictions. In turn, this observation allows us to evaluate valley splitting on a micron length scale with relatively simple Hall-bar measurements.In the third experiment we show two major improvements in our heterostructures. First, we measure valley splitting in quantum dots with varying quantum well interface sharpness with statistical significance. We then proceed to analyze the atomic composition of the quantum well interfaces in several samples using atom probe tomography and show that Ge atoms are distributed randomly in each atomic layer. Subsequently using the atom probe tomography results as input, we simulate valley splitting and show that valley splitting depends on the atomistic details of the interface and needs to be treated as a statistical distribution. We then propose a strategy to increase valley splitting on average above a chosen threshold by introducing a small concentration of Ge atoms into the quantum well. Second, all electrical measurements in this experiment are performed in isotopically purified $^{28}$Si quantum wells, which reduces the hyperfine interaction and hence increases qubit coherence times. While we do not explicitly discuss this improvement in this chapter, it is a crucial baseline for all following experiments in this thesis and for all qubit experiments using Delft grown $^{28}$Si/SiGe heterostructures. We then move to show wafer-scale improvements of the disorder landscape of Si quantum wells in our fourth experiment. There, we challenge the common approach of growing an epitaxial Si cap on the $^{28}$Si/SiGe heterostructure, by replacing the Si cap with an amorphous Si-rich layer. We compare these two heterostructues by monitoring the statistical performance of mobility, percolation density, maximum electric field before hysteresis, and single particle relaxation time and observe a statistical performance increase of the mean value and the standard deviation.In the fifth experiment we study a heterostructure with a thin quantum well and compare its statistical performance of mobility, percolation density, and charge noise with the performance of the heterostructures from the preceding experiment. Importantly, we find that misfit dislocation arising from strain relaxation are significantly reduced in thin quantum wells as confirmed by geometrical phase analysis of transmission-electron microscope images. In consequence, we observe a statistical performance increase of all key metrics in the novel heterostructure, only possible by our approach of engineering the critical material layers. Finally, we see promising simulated qubit coherence times and qubit error rates when using our charge noise results as simulation input, hinting at a practical advantage of our novel $^{28}$Si/SiGe heterostructures for quantum processors. In the last experimental chapter we demonstrate how our improved $^{28}$Si/SiGe heterostructures have enabled two key experiments in the field of spin-based quantum computing. First, we show that our purified heterostrucures may host high-quality qubits, that in turn serve as a testbed for demonstrating CMOS-based cryogenic control of silicon quantum circuits. Second, we show how our isotopically purified, low-disorder heterostructures host a 6-qubit quantum processor with high-fidelity initialization, high-fidelity gate operation, and high-fidelity readout. We conclude this thesis by highlighting key improvements of our $^{28}$Si/SiGe hetero-structures that have contributed to state-of-the-art spin qubit experiments. However, our heterostructures still require further improvements if we want to achieve error rates around 10$^{-6}$ and scale to large spin qubit arrays with more than a million qubits. Therefore, we discuss additional material changes that could further lower spin qubit error rates and we consider how to assess the uniformity of the material over different length scales, relevant when striving for larger qubit arrays.QCD/Scappucci La

Supplemental data for the paper: Multiplexed quantum transport using commercial off-the-shelf CMOS at sub-kelvin temperatures

Original dataset underlying the article "Multiplexed quantum transport using commercial off-the-shelf CMOS at sub-kelvin temperatures", to reproduce figures 3,4,5. [ Correspondence to: [email protected]

Three-Dimensional Atomic-Scale Tomography of Buried Semiconductor Heterointerfaces

Atom probes generate three-dimensional atomic-scale tomographies of material volumes corresponding to the size of modern-day solid-state devices. Here, the capabilities of atom probe tomography are evaluated to analyze buried interfaces in semiconductor heterostructures relevant for electronic and quantum devices. Employing brute-force search, the current dominant reconstruction protocol to generate tomographic three-dimensional images from Atom Probe data is advanced to its limits. Using Si/SiGe heterostructure for qubits as a model system, the authors show that it is possible to extract interface properties like roughness and width that agree with transmission electron microscopy observations on the sub-nanometer scale in an automated and highly reproducible manner. The demonstrated approach is a versatile method for atomic-scale characterization of buried interfaces in semiconductor heterostructures.QCD/Scappucci LabBUS/Quantum Delf

Wafer-scale low-disorder 2DEG in ²⁸Si/SiGe without an epitaxial Si cap

We grow 28Si/SiGe heterostructures by reduced-pressure chemical vapor deposition and terminate the stack without an epitaxial Si cap but with an amorphous Si-rich layer obtained by exposing the SiGe barrier to dichlorosilane at 500 °C. As a result, 28Si/SiGe heterostructure field-effect transistors feature a sharp semiconductor/dielectric interface and support a two-dimensional electron gas with enhanced and more uniform transport properties across a 100 mm wafer. At T = 1.7 K, we measure a high mean mobility of (1.8 ± 0.5) × 10 5 cm2/V s and a low mean percolation density of (9 ± 1) × 10 10 cm-2. From the analysis of Shubnikov-de Haas oscillations at T = 190 mK, we obtain a long mean single particle relaxation time of (8.1 ± 0.5) ps, corresponding to a mean quantum mobility and quantum level broadening of (7.5 ± 0.6) × 10 4 cm2/V s and (40 ± 3) μ eV, respectively, and a small mean Dingle ratio of (2.3 ± 0.2), indicating reduced scattering from long range impurities and a low-disorder environment for hosting high-performance spin-qubits.Accepted Author ManuscriptQCD/Scappucci LabQuTechBUS/TNO STAF

Reducing charge noise in quantum dots by using thin silicon quantum wells

Charge noise in the host semiconductor degrades the performance of spin-qubits and poses an obstacle to control large quantum processors. However, it is challenging to engineer the heterogeneous material stack of gate-defined quantum dots to improve charge noise systematically. Here, we address the semiconductor-dielectric interface and the buried quantum well of a 28Si/SiGe heterostructure and show the connection between charge noise, measured locally in quantum dots, and global disorder in the host semiconductor, measured with macroscopic Hall bars. In 5 nm thick 28Si quantum wells, we find that improvements in the scattering properties and uniformity of the two-dimensional electron gas over a 100 mm wafer correspond to a significant reduction in charge noise, with a minimum value of 0.29 ± 0.02 μeV/Hz½ at 1 Hz averaged over several quantum dots. We extrapolate the measured charge noise to simulated dephasing times to CZ-gate fidelities that improve nearly one order of magnitude. These results point to a clean and quiet crystalline environment for integrating long-lived and high-fidelity spin qubits into a larger system.Erratum DOI 10.38/s41467-023-37548-zBUS/Quantum DelftQCD/Scappucci LabQCD/Vandersypen LabBUS/TNO STAFFQN/Vandersypen La

Effect of Quantum Hall Edge Strips on Valley Splitting in Silicon Quantum Wells

We determine the energy splitting of the conduction-band valleys in two-dimensional electrons confined to low-disorder Si quantum wells. We probe the valley splitting dependence on both perpendicular magnetic field B and Hall density by performing activation energy measurements in the quantum Hall regime over a large range of filling factors. The mobility gap of the valley-split levels increases linearly with B and is strikingly independent of Hall density. The data are consistent with a transport model in which valley splitting depends on the incremental changes in density eB/h across quantum Hall edge strips, rather than the bulk density. Based on these results, we estimate that the valley splitting increases with density at a rate of 116 μeV/1011 cm-2, which is consistent with theoretical predictions for near-perfect quantum well top interfaces.QCD/Scappucci LabQuTechBusiness DevelopmentQCD/Veldhorst La