GaAs on Si epitaxy by aspect ratio trapping: analysis and reduction of defects propagating along the trench direction

The Aspect Ratio Trapping technique has been extensively evaluated for improving the quality of III-V heteroepitaxial films grown on Si, due to the potential for terminating defects at the sidewalls of SiO2 patterned trenches that enclose the growth region. However, defects propagating along the trench direction cannot be effectively confined with this technique. We studied the effect of the trench bottom geometry on the density of defects of GaAs fins, grown by metal-organic chemical vapor deposition on 300 mm Si (001) wafers inside narrow (<90 nm wide) trenches. Plan view and cross sectional Scanning Electron Microscopy and Transmission Electron Microscopy, together with High Resolution X-Ray Diffraction, were used to evaluate the crystal quality of GaAs. The prevalent defects that reach the top surface of GaAs fins are {111} twin planes propagating along the trench direction. The lowest density of twin planes, 8 108 cm 2, was achieved on “V” shaped bottom trenches, where GaAs nucleation occurs only on {111} Si planes, minimizing the interfacial energy and preventing the formation of antiphase boundaries

Chemical Mechanical Planarization for Ta-based Superconducting Quantum Devices

We report on the development of a chemical mechanical planarization (CMP) process for thick damascene Ta structures with pattern feature sizes down to 100 nm. This CMP process is the core of the fabrication sequence for scalable superconducting integrated circuits at 300 mm wafer scale. This work has established the elements of the various CMP-related design rules that can be followed by a designer for the layout of circuits that include Ta-based coplanar waveguide resonators, capacitors, and interconnects for tantalum-based qubits and single flux quantum (SFQ) circuits. The fabrication of these structures utilizes 193 nm optical lithography, along with 300 mm process tools for dielectric deposition, reactive ion etch, wet-clean, CMP and in-line metrology, all tools typical for a 300 mm wafer CMOS foundry. Process development was guided by measurements of physical and electrical characteristics of the planarized structures. Physical characterization such as atomic force microscopy across the 300 mm wafer surface showed local topography was less than 5 nm. Electrical characterization confirmed low leakage at room temperature, and less than 12% within wafer sheet resistance variation, for damascene Ta line-widths ranging from 100 nm to 3 {\mu}m. Run-to-run reproducibility was also evaluated. Effects of process integration choices including deposited thickness of Ta are discussed.Comment: 31 pages, 16 figure

Engineering of Niobium Surfaces Through Accelerated Neutral Atom Beam Technology For Quantum Applications

A major roadblock to scalable quantum computing is phase decoherence and energy relaxation caused by qubits interacting with defect-related two-level systems (TLS). Native oxides present on the surfaces of superconducting metals used in quantum devices are acknowledged to be a source of TLS that decrease qubit coherence times. Reducing microwave loss by surface engineering (i.e., replacing uncontrolled native oxide of superconducting metals with a thin, stable surface with predictable characteristics) can be a key enabler for pushing performance forward with devices of higher quality factor. In this work, we present a novel approach to replace the native oxide of niobium (typically formed in an uncontrolled fashion when its pristine surface is exposed to air) with an engineered oxide, using a room-temperature process that leverages Accelerated Neutral Atom Beam (ANAB) technology at 300 mm wafer scale. This ANAB beam is composed of a mixture of argon and oxygen, with tunable energy per atom, which is rastered across the wafer surface. The ANAB-engineered Nb-oxide thickness was found to vary from 2 nm to 6 nm depending on ANAB process parameters. Modeling of variable-energy XPS data confirm thickness and compositional control of the Nb surface oxide by the ANAB process. These results correlate well with those from transmission electron microscopy and X-ray reflectometry. Since ANAB is broadly applicable to material surfaces, the present study indicates its promise for modification of the surfaces of superconducting quantum circuits to achieve longer coherence times.Comment: 22 pages, 7 figures, will be submitted to Superconductor Science and Technology Special Focus Issue Journa

Heavily tellurium doped n-type InGaAs grown by MOCVD on 300 mm Si wafers

Tellurium has several remarkable properties that make it an attractive n-type dopant in III–V semiconductors, namely high incorporation and activation efficiency resulting in high achievable doping levels in combination with a low diffusion coefficient. However, it suffers from a strong memory effect related to its surfactant behavior that inhibits sharp junction interface formation. We report Te-doped In0.53Ga0.47As with an electron density of 8×1019 cm−3. The layers were grown by MOCVD on 300 mm Si wafers and were characterized by SIMS, XRD, Hall effect, and sheet resistivity mapping. The high active electron density and the excellent uniformity over the wafer surface make this process promising for selective regrowth of highly doped source and drain in VLSI

Growth and characterization of an In0.53Ga0.47As-based Metal-Oxide-Semiconductor Capacitor (MOSCAP) structure on 300mm on-axis Si (001) wafers by MOCVD

We report on the development of a metamorphic In0.53Ga0.47As-based heterostructure grown on 300 mm on-axis Si (001) wafers by metal-organic chemical vapor deposition (MOCVD), and the fabrication of a Metal-Oxide-Semiconductor Capacitor (MOSCAP) with C–V characteristics and interfacial trap density (Dit) values comparable to those of an equivalent structure grown on an InP substrate. A 1.15 µm thick GaAs/InP buffer with a defect density in the low 109 cm−2 range and a surface roughness rms value <2 nm was used to accommodate the large lattice mismatch between In0.53Ga0.47As and Si