Distribution of the Timing, Trigger and Control Signals in the Endcap Cathode Strip Chamber System at CMS

This paper presents the implementation of the Timing, Trigger and Control (TTC) signal distribution tree in the Cathode Strip Chamber (CSC) sub-detector of the CMS Experiment at CERN. The key electronic component, the Clock and Control Board (CCB) is described in detail, as well as the transmission of TTC signals from the top of the system down to the front-end boards

Evaluation of Data Transmission at 80MHz and 160MHz Over Backplane, Copper and Optical Links

The bunch clock frequency of the LHC accelerator at CERN is specified as 40.07897 MHz [1]. Most of the LHC experiments will utilize this frequency, its multiples or derivatives as the main frequency of data transmission for their synchronous Trigger and DAQ electronic systems. For example, the triggering system of the Cathode Strip Chamber (CSC) sub-detector at the CMS experiment comprises the onchamber anode and cathode electronics, the off-chamber boards housed in 9U crates mounted on the periphery of the Endcap iron disks, and one Track Finder (TF) crate located in the underground counting room (Fig.1). Due to the significant amount of data from the front end, the trigger patterns are multiplexed and sent from the CSC chambers over copper cables using the LVDS standard at 80 MHz. For the same reason the data patterns transmitted over backplanes in the peripheral and TF crates are also multiplexed and sent at 80MHz using the GTLP standard. Optical links from the peripheral crates to the TF are operated at 80 MHz as well. Finally, the parallel LVDS links to the Global Muon Trigger (GMT) run at 40 MHz

Commissioning of the CSC Level 1 Trigger Optical Links at CMS

The Endcap Muon (EMU) Cathode Strip Chamber (CSC) detector at the CMS experiment at CERN has been fully installed and operational since summer of 2008. The system of 180 optical links connects the middle and upper levels of the CSC Level 1 Trigger chain. Design and commissioning of all optical links present several challenges, including reliable clock distribution, link synchronization and alignment, status monitoring and system testing. We gained an extensive experience conducting various tests, participating in local and global cosmic runs and in initial stage of the LHC operation. In this paper we present our hardware, firmware and software solutions and first results of the optical link commissioning

Design Considerations for an Upgraded Track-Finding Processor in the Level-1 Endcap Muon Trigger of CMS for SLHC operations

The conceptual design for a Level-1 muon track-finder trigger for the CMS endcap muon system is proposed that can accommodate the increased particle occupancy and system constraints of the proposed SLHC accelerator upgrade and the CMS detector upgrades. A brief review of the architecture of the current track-finder for LHC trigger operation is given, with potential bottlenecks indicated for SLHC operation. The upgraded track-finding processors described here would receive as many as two track segments detected from every cathode strip chamber comprising the endcap muon system, up to a total of 18 per 60° azimuthal sector. This would dramatically improve the efficiency of the track reconstruction in a high occupancy environment over the current design. However, such an improvement would require significantly higher bandwidth and logic resources. We propose to use the fastest available serial links, running asynchronously to the machine clock to use their full bandwidth. The work of creating a firmware model for the upgraded Sector Processor is in progress; details of its implementation will be discussed. Another enhancement critical for the overall Level-1 trigger capability for physics studies in phase 2 of the SLHC is to include the inner silicon tracking systems into the design of the Level-1 trigger