14 research outputs found

    Energy efficient address assignment through minimized memory row switching

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    Yield modelling and yield enhancement for FPGAs using fault tolerance schemes

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    Optimum and heuristic synthesis of multiple word-length architectures

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    Exploration of heterogeneous FPGAs for mapping linear projection designs

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    In many applications, a reduction of the amount of the original data or a representation of the original data by a small set of variables is often required. Among many techniques, the linear projection is often chosen due to its computational attractiveness and good performance. For applications where real-time performance and flexibility to accommodate new data are required, the linear projection is implemented in field-programmable gate arrays (FPGAs) due to their fine-grain parallelism and reconfigurability properties. Currently, the optimization of such a design is considered as a separate problem from the basis calculation leading to suboptimal solutions. In this paper, we propose a novel approach that couples the calculation of the linear projection basis, the area optimization problem, and the heterogeneity exploration of modern FPGAs. The power of the proposed framework is based on the flexibility to insert information regarding the implementation requirements of the linear basis by assigning a proper prior distribution to the basis matrix. Results from real-life examples on modern FPGA devices demonstrate the effectiveness of our approach, where up to 48% reduction in the required area is achieved compared to the current approach, without any loss in the accuracy or throughput of the design

    Customizable elliptic curve cryptosystems

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    Truncation noise in fixed-point SFGs

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    Framework and tools for run-time reconfigurable designs

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