Analysis of jitter impact on high speed transmissions of wavelength-division multiplexing networks

In this study, we conduct a thorough assessment of the effect of jitter occurrence in high speed 10 Gbps and 200 GHz Wavelength-Division Multiplexing (WDM) optical network. First, we present a simulation model to study the effect of jitter presence in the proposed network and then determine the maximum amount of jitter which the network can withstand. The model is then employed to predict the types of jitter received at the end of the transmission line. For the input power level of 0 dBm and Bit Error Rate (BER) of 1E09, the observed total jitter, JT, random jitter, JR and deterministic jitter, JD is 0.2676 UI, 0.1602 UI and 0.1073 UI, respectively

An Analysis of Silicon Waveguide Phase Modulation Efficiency based on Carrier Depletion Effect

This paper highlights the study of carrier depletion effect on silicon waveguide with p-i-n diode and NPN structure. The device performance is predicted by using 2D Silvaco CAD software under different applied voltages. Device performances in terms of modulation efficiency will be discussed

Modelling and Characterization of a 14 nm Planar p-Type MOSFET Device

Coined by Gordon E. Moore through its law, a proper scaling is enforced for optimum device performance. Since 2k millennium, technology of metal gate on high-k dielectric was introduced to reduce the impact of scaling ultimatum on a transistor. In this letter, a 14nm planar p-type MOSFET device is virtually fabricated using ATHENA module and characterized for its performance evaluation using ATLAS module where both can be found in Virtual Wafer Fabrication (VWF) of Silvaco TCAD Tools. This is the continuance research from our established 32nm device simulation using HfO2/TiSi2. The findings show that the optimal value of threshold voltage (VTH), drive current (ION) and leakage current (IOFF) are -0.231507V, 72.4534 μA/um and 6.58635 pA/um respectively. The performance results also present a good switching capability of the device since the ION/IOFF ratio value is ≈106. The results of this work demonstrate that this 14nm planar p-type device possesses a good performance which can workhorse to future design and optimization

Operation mode of phase modulation based on carrier dispersion effect in p-i-n diode of silicon rib waveguide

This paper highlights the study of the carrier injection mode and the carrier depletion mode of the phase modulator. The phase modulator device has been integrated in the silicon rib waveguide by using the p-i-n diode structure. The electrical device performance is predicted by using the 2-D semiconductor package SILVACO (CAD) software under DC operation. Summarily, the phase modulator device has less sensitivity to the effective refractive index changes when operating in reverse biased or depletion mode compared to the forward biased or injection mode

Free Carrier Absorption Loss of p-i-n Silicon-On-Insulator (SOl) Phase Modulator

Silicon high-speed waveguide-integrated electro-optic modulator is one of the critical devices for on-chip optical networks. The device converts data from electrical domain to the optical domain. Most studies for high speed modulation method in Si or Si based device are based on free carrier concentration variations (injection or depletion of free carriers) which are responsible for local refractive index variations and then phase modulation of a guided wave traveling through the active region. A change in the refractive index/absorption can be achieved by injection or depletion of both electron and holes into the intrinsic region of a silicon p-i-n diode. The paper reports on the free carrier absorption (FCA) loss associated with p-i-n silicon-oninsulator (SOl) phase modulator at J... = 1.55 Ilm. The analyses include the effect of various doping concentration and injected free carrier concentration on the FCA. The simulations are realized utilizing the 2-D semiconductor simulation package SIL V ACO

VTH and ILEAK Optimization Using Taguchi Method at 32nm Bilayer Graphene PMOS

A 32nm top-gated bilayer Graphene PMOS transistor was optimized and analyzed to find the optimum value of performance parameters besides investigating the process parameter that affects the performance of the bilayer Graphene transistor the most. Firstly, ATHENA and ATLAS modules which can be found in Silvaco TCADS Tools were employed to simulate the virtual device fabrication process and to confirm the electrical features of the device, respectively. L9 Taguchi robust analysis was then applied to enhance the device process parameters for the finest threshold voltage (VTH) and lowest leakage current (ILEAK) following the International Technology Roadmap for Semiconductor (ITRS) 2011 prediction. The parameters being optimized were the Halo implantation, Halo tilting angle, S/D implantation and compensation implantation which were varied at three levels and two levels of noise factor. The noise factors include sacrificial oxide layer temperature and BPSG temperature. The results of this work show that compensation implantation and Halo implantation are the most dominant factors in affecting the VTH and ILEAK respectively. Optimized results show an excellent device performance with VTH of -0.10299V which is 0.0097% closer to ITRS2011 target and ILEAK is 0.05545673nA/um which is far lower than the prediction

Electro-Optical Modulator Performance in SOl

Since 1980's, silicon photonic devices have been extensively studied, however a submicrometre-size photonic devices have been realized only in the last few years. Silicon properties namely the transparency in the range of optical telecommunications wavelengths and high index of refraction, have enabled the fabrication of low loss submicron waveguide. Photonic devices such as splitter, coupler, and filter have been demonstrated in silicon but once the device has been fabricated, the properties of the device are predetermined. A silicon based modulator can be used to control the flow of light, where the refractive index of the silicon waveguide can be varied thus, induce a change in the transmission properties. This paper highlights the study of carrier injection effect on silicon waveguide with p-i-n diode structure integrated on Silicon-on-Insulator (SOl). The device performance is predicted using 2D Silvaco CAD software under different applied voltages at 1.55 �m

2x2 Optical Switch Based on Silicon-On-Insulator Microring Resonator

In near future, silicon-on-insulator (SOI) microring resonator are expected to be basic components for wavelength filtering and switching due to their compact size and wide free spectral range (FSR). In this paper, a 2X2 optical switch by using active microring resonator is proposed. The switch is consists of second order serially cascaded microring coupled to a pair of waveguide. The ON/OFF state of the design is control by electric signal which will vary the refractive index. The device is design to operate at 1.55μm wavelength. With a 500nm x 200nm rib dimensions, the design is proven to have single mode behaviour. Finite-Difference Time-Domain (FDTD) method simulation by RSOFT software is use to characterize the device performance. The results show that the 2X2 optical switch proposed can be an efficient device to be functioning in WDM application

Effect of Low Temperature on The Fabrication of Microring Resonator by Wet Etching

Research related to semiconductor devices often relies on wafer fabrication. The fabrication of Silicon (Si) based devices by anisotropic wet etching can be affected by many etching parameters such as etching temperature, crystal orientation and percent of composition. Most of the anisotropic wet etchings by KOH solution done before were conducted at temperature over 70°C. We found that the temperatures are not suitable to fabricate ring waveguide as the waveguide wall will collapse at such high temperature. This study reports the etching characteristics of Si in KOH solution with 35% concentration at the temperature below 70°C. The etched wafer is targeted to be the basic structure for Microring Resonators (MRRs) based devices. This technique provides not only lower cost as compared to other etching technique, but also simple preparation. We found that low temperature manage to mold a good ring waveguide with low tendency to form rectangular structure due to crystal orientation. At 40°C, the best waveguide formation was obtained with a smooth waveguide surface, experiencing an etching rate of 0.066 μ min-1 and an appreciable ring waveguide structure. The effect of the low temperature on the fabrication of the MRRs devices has been investigated and studied

After 75 Years of the transistor: an age of neuromorphic computing [women in electronic devices]

Aligned to IEEE’s mission to foster diversity, equity, and inclusion in technological innovation and excellence, the IEEE Electron Devices Society (EDS) has committed to increase the percentage of EDS female membership by 2% annually over the next five years. The aim is to create a vibrant and inclusive community of both women and men collectively using their diverse talents to innovate for the benefit of humanity. In this spirit, this news column is contributed by Women in EDS