Matrix Operations on Reconfigurable Systems

This article introduces the new ideas and techniques of algorithm-architecture codesign (AA codesign) for customized computation on reconfigurable systems. This approach, enabled by recent advances in reconfigurable hardware, notably the field programmable gate arrays (FPGAs), integrates the design of algorithms and architectures for improving computation performance and resource utilization. It utilizes software-hardware codesign techniques, but distinguishes itself in algorithm-architecture co-configuration, ending the isolation between algorithm and architecture designs. We report our investigation and experiments for certain structured matrix operations. The new approach is shown effective, for instance, in power reduction without compromising computation performance, or in accuracy improvement without using additional resources. This denotes a significant shift from the conventional tradeoff between efficiency and accuracy as well as the tradeoff between computation performance and resource consumption

Efficient function evaluations with lookup tables for structured matrix operations

A hardware efficient approach is introduced for elementary function evaluations in certain structured matrix computations. It is a comprehensive approach that utilizes lookup tables for compactness, employs interpolations with adders and multipliers for their adaptivity to non-tabulated values and, more distinctively, exploits the function properties and the matrix structures to claim better control over numerical dynamic ranges. We demonstrate the effectiveness of the approach with simulation and synthesis results on evaluating, in particular, the cosine function, the exponential function and the zero-order Bessel function of the first kind