128 research outputs found

    Degradation of MONOCULM 1 by APC/CTAD1 regulates rice tillering

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    A rice tiller is a specialized grain-bearing branch that contributes greatly to grain yield. The MONOCULM 1 (MOC1) gene is the first identified key regulator controlling rice tiller number; however, the underlying mechanism remains to be elucidated. Here we report a novel rice gene, Tillering and Dwarf 1 (TAD1), which encodes a co-activator of the anaphase-promoting complex (APC/C), a multi-subunit E3 ligase. Although the elucidation of co-activators and individual subunits of plant APC/C involved in regulating plant development have emerged recently, the understanding of whether and how this large cell-cycle machinery controls plant development is still very limited. Our study demonstrates that TAD1 interacts with MOC1, forms a complex with OsAPC10 and functions as a co-activator of APC/C to target MOC1 for degradation in a cell-cycle-dependent manner. Our findings uncovered a new mechanism underlying shoot branching and shed light on the understanding of how the cell-cycle machinery regulates plant architecture

    Univ. of Kiel’s MIMOLA System

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    Code Generation for Embedded Processors: An Introduction, chapter 1

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    1 New, exible target technologies As the tendency towards more complex electronic systems continues, many of these systems are equipped with embedded processors. For example, such processors can be found in cars, and i

    Synthesis of Communicating Controllers for Concurrent Hardware/Software Systems

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    Two main aspects in hardware/software co-design are hardware/software partitioning and co-synthesis. Most co-design approaches work only on one of these problems. In this paper, an approach coupling hardware /software partitioning and co-synthesis will be presented, working fully-automatic. The techniques have been integrated in the co-design tool Cool 1 supporting the complete design flow from system specification to board-level implementation for multi-processor and multi-ASIC target architectures for data-flow dominated applications. 1 Introduction Most approaches in co-design work either on techniques for partitioning or co-synthesis using manual partitioning. Hardware/software partitioning has been explored intensively, using different algorithms to solve this complex optimization problem, e.g. dynamic programming, evolutionary strategies, mixed integer linear programming or several heuristic approaches. Techniques for interface and communication synthesis have been explored f..

    Code Generation for Embedded Processors: An Introduction

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    Introduction P. Marwedel 1 New, flexible target technologies As the tendency towards more complex electronic systems continues, many of these systems are equipped with embedded processors. For example, such processors can be found in cars, and in audio-, video-, and telecommunication-equipment. Essential advantages of these processors include their high flexibility, short design time and (in the case of off-the-shelf processors) full-custom layout quality. Furthermore, they allow an easy implementation of optional product features as well as easy design correction and upgrading. Furthermore, processors are frequently used in cases where the systems must be extremely dependable 1 [32]. In such cases, the re-use of the design of an off-the-shelf processor greatly simplifies dependability analysis. This contrasts with the limitations of application-specific circuits (ASICs): due to their low flexibility, the cost for the desi

    Integrated Scheduling and Binding: A Synthesis Approach for Design Space Exploration

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    Synthesis of digital systems, involves a number of tasks ranging from scheduling to generating interconnections. The interrelationship between these tasks implies that good designs can only be generated by considering the overall impact of a design decision. The approach presented in this paper provides a framework for integrating scheduling decisions with binding decisions. The methodology supports allocation of a wider mix of operator modules and covers the design space more effectively. The process itse1.f can be described as incremental synthesis and is thus well-suited for applications involving partial pre-synthesized structures. 1

    Graph based retargetable microcode compilation in the MIMOLA design system

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    Introduction and Motivation

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