A Survey of Circuit Innovations in Ferroelectric Random-Access Memories

This paper surveys circuit innovations in ferroelectric memories at three circuit levels: memory cell, sensing, and architecture. A ferroelectric memory cell consists of at least one ferroelectric capacitor, where binary data are stored, and one or two transistors that either allow access to the capacitor or amplify its content for a read operation. Once a cell is accessed for a read operation, its data are presented in the form of an analog signal to a sense amplifier, where it is compared against a reference voltage to determine its logic level. The circui

Locally connected VLSI architectures for the Viterbi algorithm

Abstract-The Viterbi algorithm is a well-established technique for channel and source decoding in high performance digital communica-tion systems. Implementations of the Viterbi algorithm on three types of locally connected processor arrays are described. This restriction is motivated by the fact that both the cost and performance metrics of VLSI favor architectures in which on-chip interprocessor communi-cation is localized. Each of the structures presented can accommodate arbitrary alphabet sizes and algorithm memory lengths. The relative performance tradeoff s available to the designer are discussed in the context of previous work. I

Implementation Issues for High-Bandwidth FieldProgrammable Analog Arrays

This paper is a tutorial introduction to field-programmable analog arrays, as well as a review of existing field-programmable analog array architectures, of both educational and industrial origin. Circuit issues relevant to the development of high-bandwidth FPAAs are presented. A current conveyor-based architecture, which promises to achieve video bandwidths, is described. Test results are presented for the CMOS current conveyor-based FPAA building block, with programmable transconductors and capacitors. Measurements indicate bandwidths in excess of 10MHz, and functionality of amplifiers, integrators, differentiators, and adders. The die area is 1.5mm x 3.5mm in a 0.8μm CMOS technology. 1

Look-Up Tables (LUTs) for Multiple-Valued

The use of Look-Up Tables (LUTs) is extended from binary to multiple-valued logic (MVL) circuits. A multiplevalued LUT can be implemented using both current-mode and voltage-mode techniques, reducing the transistor count to half compared to that of a binary implementation. Two main applications for multiple-valued LUTs are multiple-valued FPGAs and intelligent memories. An FPGA uses a LUT as a generic logic block to provide programmability. In an intelligent memory, a multiplevalued LUT is added in the Y-decoder section to facilitate simple mathematical operations on the stored digits. An FFT operation is used as an example in this paper to illustrate how a multiple-valued LUT can be beneficial

Rapid Bacterial Detection via an All-Electronic CMOS Biosensor.

The timely and accurate diagnosis of infectious diseases is one of the greatest challenges currently facing modern medicine. The development of innovative techniques for the rapid and accurate identification of bacterial pathogens in point-of-care facilities using low-cost, portable instruments is essential. We have developed a novel all-electronic biosensor that is able to identify bacteria in less than ten minutes. This technology exploits bacteriocins, protein toxins naturally produced by bacteria, as the selective biological detection element. The bacteriocins are integrated with an array of potassium-selective sensors in Complementary Metal Oxide Semiconductor technology to provide an inexpensive bacterial biosensor. An electronic platform connects the CMOS sensor to a computer for processing and real-time visualization. We have used this technology to successfully identify both Gram-positive and Gram-negative bacteria commonly found in human infections

Towards a VLSI Architecture for Interpolation-Based Soft-Decision Reed-Solomon Decoders

The Koetter-Vardy algorithm is an algebraic soft-decision decoder for Reed-Solomon codes which is based on the Guruswami-Sudan list decoder. There are three main steps: 1) multiplicity calculation, 2) interpolation and 3) root finding. The Koetter-Vardy algorithm is challenging to implement due to the high cost of interpolation. We propose a VLSI-oriented improvement to the interpolation algorithm that uses a transformation of the received word to reduce the number of iterations. We show how to reduce the the memory requirements and give an efficient VLSI implementation for the Hasse derivative