Block-Anti-Circulant Unbalanced Oil and Vinegar

We introduce a new technique for compressing the public keys of the UOV signature scheme that makes use of block-anti-circulant matrices. These matrices admit a compact representation as for every block, the remaining elements can be inferred from the first row. This space saving translates to the public key, which as a result of this technique can be shrunk by a small integer factor. We propose parameters sets that take into account several important attacks

Efficient decryption algorithms for extension field cancellation type encryption schemes

Extension Field Cancellation (EFC) was proposed by Alan et al. at PQCrypto 2016 as a new trapdoor for constructing secure multivariate encryption cryptographic schemes. Along with this trapdoor, two schemes EFC−p and EFC−pt2 that apply this trapdoor and some modifiers were proposed. Though their security seems to be high enough, their decryption efficiency has room for improvement. In this paper, we introduce a new and more efficient decryption approach for EFC−p and EFC−pt2, which manages to avoid all redundant computation involved in the original decryption algorithms, and theoretically speed up the decryption process of EFC−p and EFC−pt2 by around 3.4 and 8.5 times, respectively, under 128-bit security parameters with our new designed private keys for them. Meanwhile, our approach does not interfere with the public key, so the security remains the same. The implementation results of both decryption algorithms for EFC−p and EFC−pt2 are also provided

Efficient Hardware Implementation of MQ Asymmetric Cipher PMI+ on FPGAs

PMI+ is a Multivariate Quadratic (MQ) public key algorithm used for encryption and decryption operations, and belongs to post quantum cryptography.We designs a hardware on FPGAs to efficiently implement PMI+ in this paper.Our main contributions are that,firstly, a hardware architecture of encryption and decryption of PMI+ is developed, and description of corresponding hardware algorithm is proposed;secondly, basic arithmetic units are implemented with higher efficiency that multiplication, squaring, vector dot product and power operation are implemented in full parallel;and thirdly, an optimized implementation for core module, including optimized large power operation, is achieved. The encryption and decryption hardware of PMI+ is efficiently realized on FPGA by the above optimization and improvement.It is verified by experiments that the designed hardware can complete an encryption operation within 497 clock cycles, and the clock frequency can be up to 145.6MHz,and the designed hardware can complete a decryption operation within 438 clock cycles wherein the clock frequency can be up to 37.04MHz