Real-Time Decoding for Fault-Tolerant Quantum Computing: Progress, Challenges and Outlook

Quantum computing is poised to solve practically useful problems which are computationally intractable for classical supercomputers. However, the current generation of quantum computers are limited by errors that may only partially be mitigated by developing higher-quality qubits. Quantum error correction (QEC) will thus be necessary to ensure fault tolerance. QEC protects the logical information by cyclically measuring syndrome information about the errors. An essential part of QEC is the decoder, which uses the syndrome to compute the likely effect of the errors on the logical degrees of freedom and provide a tentative correction. The decoder must be accurate, fast enough to keep pace with the QEC cycle (e.g., on a microsecond timescale for superconducting qubits) and with hard real-time system integration to support logical operations. As such, real-time decoding is essential to realize fault-tolerant quantum computing and to achieve quantum advantage. In this work, we highlight some of the key challenges facing the implementation of real-time decoders while providing a succinct summary of the progress to-date. Furthermore, we lay out our perspective for the future development and provide a possible roadmap for the field of real-time decoding in the next few years. As the quantum hardware is anticipated to scale up, this perspective article will provide a guidance for researchers, focusing on the most pressing issues in real-time decoding and facilitating the development of solutions across quantum and computer science

Neural-Network Decoders for Quantum Error Correction using Surface Codes:A Space Exploration of the Hardware Cost-Performance Trade-Offs

Quantum Error Correction (QEC) is required in quantum computers to mitigate the effect of errors on physical qubits. When adopting a QEC scheme based on surface codes, error decoding is the most computationally expensive task in the classical electronic back-end. Decoders employing neural networks (NN) are well-suited for this task but their hardware implementation has not been presented yet. This work presents a space exploration of fully-connected feed-forward NN decoders for small distance surface codes. The goal is to optimize the neural network for high decoding performance, while keeping a minimalistic hardware implementation. This is needed to meet the tight delay constraints of real-time surface code decoding. We demonstrate that hardware based NN-decoders can achieve high decoding performance comparable to other state-of-the-art decoding algorithms whilst being well below the tight delay requirements $(\approx 440\ \mathrm{ns})$ of current solid-state qubit technologies for both ASIC designs $(<30\ \mathrm{ns})$ and FPGA implementations $(<90\ \mathrm{ns})$. These results designates NN-decoders as fitting candidates for an integrated hardware implementation in future large-scale quantum computers.Comment: 19 pages, 21 figures, 5 paper

Cryo-CMOS for Analog/Mixed-Signal Circuits and Systems

CMOS circuits operating at cryogenic temperature (cryo-CMOS) are required in several low-temperature applications. A compelling example is the electronic interface for quantum processors, which must reside very close to the cryogenic quantum devices it serves, and hence operate at the same temperature, so as to enable practical large-scale quantum computers. Such cryo-CMOS circuits must achieve extremely high performance while dissipating minimum power to be compatible with existing cryogenic refrigerators. These requirements asks for cryo-CMOS electronics on par with or even exceeding their room temperature counterparts. This paper overviews the challenges and the opportunities in designing cryo-CMOS circuits, with a focus on analog and mixed-signal circuits, such as voltage references and data converters