A W-Band On-Wafer Active Load-Pull System Based on Down-Conversion Techniques

A new W-band active load-pull system is presented. It is the first load-pull system to implement a 94 GHz load by means of an active loop exploiting frequency conversion techniques. The active loop configuration demonstrates a number of advantages that overcome the typical limitations of W-band passive tuners or conventional active open loop techniques in a cost effective way: load reflection coefficients Γ L as high as 0.95 in magnitude can be achieved at 94 GHz, thus providing a nearly full coverage of the Smith Chart. Possible applications of the setup include technology assessment, large-signal device model verification at sub-THz frequencies, and W-band MMIC design and characterization. The availability of direct and accurate load-pull measurements at W-band should prove an asset in the development of sub-THz integrated circuits. First measure- ments performed on high performance InP double heterojunction bipolar transistors (DHBTs) and GaN high electron mobility transistors (HEMTs) are presente

Г-L intervalley separation and electron mobility in GaAsSb grown on InP: Transport comparison with the GaInAs and GaInAsSb alloys

GaAs0.51Sb0.49 is lattice-matched to InP and finds electron transport applications in base or absorber layers in high-speed heterostructure bipolar transistors or photodiodes, because its staggered (“type-II”) band alignment with InP favors electron injection across abrupt heterojunctions. Little remains known about electron transport properties and band structure details of GaAsxSb1−x near x = 0.5. Particularly, based on the Γ-L intervalley separation in binary constituents (ΔΓL = 84 meV in GaSb and 290 meV in GaAs at 300 K), interpolation suggests a low Γ-L separation in GaAs0.51Sb0.49 before considering energy gap bowing effects. To gain insight into electron transport in GaAs0.51Sb0.49, we characterized experimental Hall electron mobilities vs carrier concentration at 300 and 77 K in n-type GaAs0.51Sb0.49, Ga0.47In0.53As, and Ga0.76In0.24As0.67Sb0.33 alloys nearly matched to InP. In marked contrast to the other two alloys, GaAs0.51Sb0.49 exhibits a sharp rise in 77 K electron mobility, which evidences L-valley de-population for lower electron concentrations. A two-band transport analysis reveals a Γ-L valley separation ΔΓL = 91 meV at 77 K, significantly lower than values recommended in the literature. Based on the reported temperature variations of ΔΓL in GaAs and GaSb, 84 < ΔΓL < 95 meV is expected at 300 K. The corresponding GaAsxSb1−x L-valley bowing parameter is cL = 1.63 eV, significantly higher than the 1.1–1.2 eV recommended in the literature. In contrast to GaAsxSb1−x, GaInAsSb grown on InP displays a strong alloy scattering, which limits its low-temperature electron mobility. The direct gap GaAs0.51Sb0.49 mixed group-V ternary alloy lattice-matched to InP is characterized by a staggered (“type-II”) band alignment that allows direct electron injection into InP across abrupt heterojunctions.1,2 As such, it finds electron transport applications in devices such as NpN double heterojunction bipolar transistors (DHBTs)3 and unitraveling carrier photodiodes (UTC-PDs).4 Despite increasing device uses over the last two decades, relatively little remains known about electron transport properties and the band structure of GaAsxSb1−x near x ∼ 0.5. Based on the known Γ-L intervalley separation in binary constituents (ΔΓL = 84 meV in GaSb5 and 290 meV in GaAs6 at 300 K, Table I), interpolation suggests a low Γ-L separation in GaAs0.51Sb0.49, even before considering potential alloy gap bowing effects. While linear interpolation yields ΔΓL = 187 meV, Adachi7 and Vurgaftman et al.8 recommend 181 and 223 meV, respectively. Due to the lack of experimental data around x ∼ 0.5, theoretical works involving GaAs0.51Sb0.49 rely on a variety of values: Tea and Aniel9 and Ferry10 used ΔΓL = 121 meV, while Wen et al. selected 196 meV.11 Bennett and Hung showed that because of the low ΔΓL separation and the high L-valley density of states in GaSb, more carriers are always present in the L-valley than the Г-valley at 300 K.12 We find that GaAs0.51Sb0.49 behaves similarly. Simple estimates using non-degenerate statistics at 300 K suggest the L-valley in GaAs0.51Sb0.49 would be significantly populated, even with a Γ-L separation as high as 220 meV (which is more than two times higher than our experimentally extracted ΔΓL value).ISSN:0003-6951ISSN:1077-311

Impact of Reduced Gate‐to‐Source Spacing on InP HEMT Performance

InP–based HEMTs with an offset gate enable higher maximum oscillation frequency (fMAX) values because of the resulting reduction in gate–to–source resistance. Following this approach, we show improved DC characteristics and cutoff frequencies (fT/fMAX > 410/710 GHz with LG = 50 nm) with respect to centered gate devices. However, HEMTs with an offset gate show degraded noise performances compared to centered gate devices because of a higher gate leakage current. Our results show that offsetting the gate closer to the source is not desirable for ultra–low noise performance.ISSN:1862-6300ISSN:1862-6319ISSN:0031-8965ISSN:1521-396

High-Speed Steep-Slope GaInAs Impact Ionization MOSFETs (I-MOS) With SS = 1.25 mV/dec - Part II: Dynamic Switching and RF Performance

Part I of this work described narrow bandgap GaInAs-based I-MOS devices with a minimum steep slope SSmin = 1.25 mV/dec maintained over 4 orders of magnitude in drain current, ION/IOFF ratios >106 at 300 K (>109 at 15 K), and low operating voltages for a gate length of LG = 100 nm. Part II focuses on the device time-domain switching capabilities and RF performance. Digital switching tests using a hybrid connected inverter reveal excellent capabilities for high clock rate operation. Simple circuit estimates indicate that the present 100 nm GaInAs I-MOS can operate with clock frequencies >10 GHz. The impact-ionization-induced hysteresis in the ID – VGS I-MOS characteristics does not play any role in dynamic switching of a digital inverter: the n -channel pull-down transistor turns on with a steep slope, but turns off classically with a higher threshold voltage which reduces the dynamic power dissipation per switching cycle. Factors impacting GaInAs I-MOS reliability are considered, and a physically motivated approach to enhance the reliability of III–V MOSFETs is proposed. We show that GaInAs-based I-MOS devices offer high analog cutoff frequencies and low-noise characteristics, suggesting applicability for digital and RF applications on a single technological platform. When benchmarked against other steep-slope technologies, GaInAs I-MOS shows the strongest steep slope, competitive ION/IOFF ratios, and lowest operating voltage of any I-MOS transistor to date, without any back-gate/substrate bias.ISSN:0018-9383ISSN:1557-964

InAs Channel Inset Effects on the DC, RF, and Noise Properties of InP pHEMTs

ISSN:0018-9383ISSN:1557-964

High-Speed Steep-Slope GaInAs Impact Ionization MOSFETs (I-MOS) With SS = 1.25 mV/dec - Part I: Material and Device Characterization, DC Performance, and Simulation

Digital electronics power consumption evolved into a major concern: at the current pace, general-purpose computing energy consumption will exceed global energy production before 2045. The principal approach to curbing energy consumption in digital applications calls for ``steep-slope'' devices with an inverse subthreshold slope (SS) parameter well below the ``ln(10)·kT/q'' limit of conventional electronics (60 mV/dec at 300 K). Impact ionization MOSFETs (I-MOS) provide an avenue for steep-slope device realization. High-mobility narrow gap III-V semiconductor channel materials have not yet been investigated for I-MOS applications. We hereby report E-mode narrow bandgap GaInAs-based I-MOS devices with an SS of 1.25 mV/dec maintained over five orders of magnitude in drain current and Ion / Ioff ratios >10⁶ at 300 K (>10⁹ at 15 K) for a gate length of LG = 100 nm. Part I of this work focuses on the materials and device fabrication and analysis, device dc characterization, and modeling. The present GaInAs devices are the first I-MOS transistors to display a robust steep-slope effect at low voltages VDS < 1.9 V at 300 K and <1 V at 15 K. Part II describes the dynamic switching (including clarifications on the role of hysteresis) and RF characteristics of GaInAs I-MOS devices and benchmarks them with respect to other steep-slope technologies.ISSN:0018-9383ISSN:1557-964