Monolithic electronic-photonic integration in state-of-the-art CMOS processes

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Cataloged from student submitted PDF version of thesis.Includes bibliographical references (p. 388-407).As silicon CMOS transistors have scaled, increasing the density and energy efficiency of computation on a single chip, the off-chip communication link to memory has emerged as the major bottleneck within modern processors. Photonic devices promise to break this bottleneck with superior bandwidth-density and energy-efficiency. Initial work by many research groups to adapt photonic device designs to a silicon-based material platform demonstrated suitable independent performance for such links. However, electronic-photonic integration attempts to date have been limited by the high cost and complexity associated with modifying CMOS platforms suitable for modern high-performance computing applications. In this work, we instead utilize existing state-of-the-art electronic CMOS processes to fabricate integrated photonics by: modifying designs to match the existing process; preparing a design-rule compliant layout within industry-standard CAD tools; and locally-removing the handle silicon substrate in the photonic region through post-processing. This effort has resulted in the fabrication of seven test chips from two major foundries in 28, 45, 65 and 90 nm CMOS processes. Of these efforts, a single die fabricated through a widely available 45nm SOI-CMOS mask-share foundry with integrated waveguides with 3.7 dB/cm propagation loss alongside unmodified electronics with less than 5 ps inverter stage delay serves as a proof-of-concept for this approach. Demonstrated photonic devices include high-extinction carrier-injection modulators, 8-channel wavelength division multiplexing filter banks and low-efficiency silicon germanium photodetectors. Simultaneous electronic-photonic functionality is verified by recording a 600 Mb/s eye diagram from a resonant modulator driven by integrated digital circuits. Initial work towards photonic device integration within the peripheral CMOS flow of a memory process that has resulted in polysilicon waveguide propagation losses of 6.4 dB/cm will also be presented.by Jason S. Orcutt.Ph.D

Flaw-limited transport in germanium-on-silicon photodiodes

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.Includes bibliographical references (p. 201-206).Epitaxial germanium growth on silicon substrates has enabled a new class of photodiodes that can be integrated with traditional silicon electronics. Previous workers using lowthroughput growth techniques have demonstrated device functionality sufficient for many applications. To enable commercial integration, however, similar performance must be achieved using high throughput epitaxy. In this work, the current performance of germanium-on-silicon photodiodes fabricated by MIT colleagues using one such technique, low pressure chemical vapor deposition (LPCVD), is analyzed. The measured electrical characteristics of multiple diode geometries are fit to finite-element simulation to extract bulk and surface generation rates as a function of bias voltage. The extracted rates are then fit in conjunction with known states from the germanium defect literature to find the densities and field dependant cross sections of physical flaws believed to limit this promising class of devices. General interest photodiode performance is then quantified by optoelectronic measurements and analyzed in the context of the flaw limited transport. Device applicability for integration with an existing photonic sampling system is analyzed and intersymbol interference, noise and linearity metrics are measured and discussed. In conclusion, a pathway for improved devices based upon improved fabrication techniques to reduce identified flaw densities combined with changes in device design is proposed.by Jason S. Orcutt.S.M

High-Q CMOS-integrated photonic crystal microcavity devices

Integrated optical resonators are necessary or beneficial in realizations of various functions in scaled photonic platforms, including filtering, modulation, and detection in classical communication systems, optical sensing, as well as addressing and control of solid state emitters for quantum technologies. Although photonic crystal (PhC) microresonators can be advantageous to the more commonly used microring devices due to the former's low mode volumes, fabrication of PhC cavities has typically relied on electron-beam lithography, which precludes integration with large-scale and reproducible CMOS fabrication. Here, we demonstrate wavelength-scale polycrystalline silicon (pSi) PhC microresonators with Qs up to 60,000 fabricated within a bulk CMOS process. Quasi-1D resonators in lateral p-i-n structures allow for resonant defect-state photodetection in all-silicon devices, exhibiting voltage-dependent quantum efficiencies in the range of a few 10 s of %, few-GHz bandwidths, and low dark currents, in devices with loaded Qs in the range of 4,300–9,300; one device, for example, exhibited a loaded Q of 4,300, 25% quantum efficiency (corresponding to a responsivity of 0.31 A/W), 3 GHz bandwidth, and 30 nA dark current at a reverse bias of 30 V. This work demonstrates the possibility for practical integration of PhC microresonators with active electro-optic capability into large-scale silicon photonic systems.United States. Defense Advanced Research Projects Agency. Photonically Optimized Embedded MicroprocessorsUnited States. Dept. of Energy (Science Graduate Fellowship

Microbial activity in the marine deep biosphere: progress and prospects

The vast marine deep biosphere consists of microbial habitats within sediment, pore waters, upper basaltic crust and the fluids that circulate throughout it. A wide range of temperature, pressure, pH, and electron donor and acceptor conditions exists—all of which can combine to affect carbon and nutrient cycling and result in gradients on spatial scales ranging from millimeters to kilometers. Diverse and mostly uncharacterized microorganisms live in these habitats, and potentially play a role in mediating global scale biogeochemical processes. Quantifying the rates at which microbial activity in the subsurface occurs is a challenging endeavor, yet developing an understanding of these rates is essential to determine the impact of subsurface life on Earth\u27s global biogeochemical cycles, and for understanding how microorganisms in these “extreme” environments survive (or even thrive). Here, we synthesize recent advances and discoveries pertaining to microbial activity in the marine deep subsurface, and we highlight topics about which there is still little understanding and suggest potential paths forward to address them. This publication is the result of a workshop held in August 2012 by the NSF-funded Center for Dark Energy Biosphere Investigations (C-DEBI) “theme team” on microbial activity (www.darkenergybiosphere.org)

Microbial activity in the marine deep biosphere: progress and prospects

The vast marine deep biosphere consists of microbial habitats within sediment, pore waters, upper basaltic crust and the fluids that circulate throughout it. A wide range of temperature, pressure, pH, and electron donor and acceptor conditions exists—all of which can combine to affect carbon and nutrient cycling and result in gradients on spatial scales ranging from millimeters to kilometers. Diverse and mostly uncharacterized microorganisms live in these habitats, and potentially play a role in mediating global scale biogeochemical processes. Quantifying the rates at which microbial activity in the subsurface occurs is a challenging endeavor, yet developing an understanding of these rates is essential to determine the impact of subsurface life on Earth's global biogeochemical cycles, and for understanding how microorganisms in these “extreme” environments survive (or even thrive). Here, we synthesize recent advances and discoveries pertaining to microbial activity in the marine deep subsurface, and we highlight topics about which there is still little understanding and suggest potential paths forward to address them.This is the publisher’s final pdf. The published article is copyrighted by the author(s) and published by Frontiers Research Foundation. The published article can be found at: http://www.frontiersin.org/Microbiology.Keywords: Subsurface microbiology, Biogeochemistry, C-DEBI, Deep biosphere, IODP, Sediment, Oceanic crustKeywords: Subsurface microbiology, Biogeochemistry, C-DEBI, Deep biosphere, IODP, Sediment, Oceanic crus

Photonic Device Layout Within the Foundry CMOS Design Environment

A design methodology to layout photonic devices within standard electronic complementary metal-oxide-semiconductor (CMOS) foundry data preparation flows is described. This platform has enabled the fabrication of designs in three foundry scaled-CMOS processes from two semiconductor manufacturers.United States. Defense Advanced Research Projects Agency (DARPA)National Science Foundation (U.S.

Integration of silicon photonics into electronic processes

Front-end monolithic integration has enabled photonic devices to be fabricated in bulk and thin-SOI CMOS as well as DRAM electronics processes. Utilizing the CMOS generic process model, integration was accomplished on multi-project wafers that were shared by standard electronic customers without requiring in-foundry process changes. Simple die or wafer-level post-processing has enabled low-loss waveguides by the removal of the substrate within photonic regions. The custom-process model of the DRAM industry instead enabled optimization of the photonic device fabrication process and the potential elimination of post-processing requirements. Integrated singlecrystalline silicon waveguide loss of ~3 dB/cm has been achieved within a 45nm thin-SOI CMOS process that is currently used to manufacture microprocessors [1]. A fully monolithic photonic transmitter including a pseudo-random bit sequence (PRBS) generating digital backend was also demonstrated within this process [1]. The constraints of zero-change integration have limited achieved polysilicon waveguide loss to ~50 dB/cm with commercially available bulk CMOS processes [2]. Custom polysilicon deposition and processing conditions available for DRAM integration have also led to the demonstration of ~6 dB/cm loss waveguides suitable for integration within electronics processes utilizing bulk silicon starting substrates [3]. An overview of required process features, device design guidelines and integration methodology tradeoffs will be presented. Relevant device metrics of area and energy efficiency as well as achievable photonic device performance will be presented within the context of monolithic front-end integration within state-ofthe- art electronics processes. Applications of this research towards the implementation of a computer system utilizing photonic interconnect for core-to-memory communication will also be discussed.United States. Defense Advanced Research Projects AgencyNational Science Foundation (U.S.) (NSF Graduate Research Fellowship

Tolerance analysis for efficient MMI devices in silicon photonics

Silicon is considered a promising platform for photonic integrated circuits as they can be fabricated in state-of-the-art electronics foundaries with integrated CMOS electronics. While much of the existing work on CMOS photonics has used directional couplers for power splitting, multimode interference (MMI) devices may have relaxed fabrication requirements and smaller footprints, potentially energy efficient designs. They have already been used as 1x2 splitters, 2x1 combiners in Quadrature Phase Shift Keying modulators, and 3-dB couplers among others. In this work, 3-dB, butterfly and cross MMI couplers are realized on bulk CMOS technology. Footprints from around 40um2 to 200 um2 are obtained. MMI tolerances to manufacturing process and bandwidth are analyzed and tested showing the robustness of the MMI devices.Fundación Caja MadridSpain. Ministerio de Economía y Competitividad (project TEC2012-37983-C03-02)Spain. Ministerio de Economía y Competitividad (grant EEBB- 1-13-07511)Spain. Ministerio de Educación y Ciencia (grant PRX12/00007

Spoked-ring microcavities: enabling seamless integration of nanophotonics in unmodified advanced CMOS microelectronics chips

We present the spoked-ring microcavity, a nanophotonic building block enabling energy-efficient, active photonics in unmodified, advanced CMOS microelectronics processes. The cavity is realized in the IBM 45nm SOI CMOS process – the same process used to make many commercially available microprocessors including the IBM Power7 and Sony Playstation 3 processors. In advanced SOI CMOS processes, no partial etch steps and no vertical junctions are available, which limits the types of optical cavities that can be used for active nanophotonics. To enable efficient active devices with no process modifications, we designed a novel spoked-ring microcavity which is fully compatible with the constraints of the process. As a modulator, the device leverages the sub-100nm lithography resolution of the process to create radially extending p-n junctions, providing high optical fill factor depletion-mode modulation and thereby eliminating the need for a vertical junction. The device is made entirely in the transistor active layer, low-loss crystalline silicon, which eliminates the need for a partial etch commonly used to create ridge cavities. In this work, we present the full optical and electrical design of the cavity including rigorous mode solver and FDTD simulations to design the Qlimiting electrical contacts and the coupling/excitation. We address the layout of active photonics within the mask set of a standard advanced CMOS process and show that high-performance photonic devices can be seamlessly monolithically integrated alongside electronics on the same chip. The present designs enable monolithically integrated optoelectronic transceivers on a single advanced CMOS chip, without requiring any process changes, enabling the penetration of photonics into the microprocessor.United States. Defense Advanced Research Projects Agency (DARPA POEM program award HR0011-11-C-0100)United States. Defense Advanced Research Projects Agency (DARPA POEM program award HR0011-11-9-0009)National Science Foundation (U.S.) (Graduate Research Fellowship Program (GRFP) award

BUILDING MANY-CORE PROCESSOR-TO-DRAM NETWORKS WITH MONOLITHIC CMOS SILICON PHOTONICS

Silicon photonics is a promising technology for addressing memory bandwidth limitations in future many-core processors. This article first introduces a new monolithic silicon-photonic technology, which uses a standard bulk CMOS process to reduce costs and improve energy efficiency, and then explores the logical and physical implications of leveraging this technology in processor-to-memory networks.DARPA/MTO (award W911NF-06- 1-0449