Digital tanlock loop architecture with no delay

This article proposes a new architecture for a digital tanlock loop which eliminates the time-delay block. The �=2 (rad) phase shift relationship between the two channels, which is generated by the delay block in the conventional timedelay digital tanlock loop (TDTL), is preserved using two quadrature sampling signals for the loop channels. The proposed system outperformed the original TDTL architecture, when both systems were tested with frequency shift keying input signal. The new system demonstrated better linearity and acquisition speed as well as improved noise performance compared with the original TDTL architecture. Furthermore, the removal of the time-delay block enables all processing to be digitally performed, which reduces the implementation complexity. Both the original TDTL and the new architecture without the delay block were modelled and simulated using ATLAB/Simulink. Implementation issues, including complexity and relation to simulation of both architectures, are also addressed

Performance evaluation of the time delay digital tanlock loop architectures

This article presents the architectures, theoretical analyses and testing results of modified time delay digital tanlock loop (TDTLs) system. The modifications to the original TDTL architecture were introduced to overcome some of the limitations of the original TDTL and to enhance the overall performance of the particular systems. The limitations addressed in this article include the non-linearity of the phase detector, the restricted width of the locking range and the overall system acquisition speed. Each of the modified architectures was tested by subjecting the system to sudden positive and negative frequency steps and comparing its response with that of the original TDTL. In addition, the performance of all the architectures was evaluated under noise-free as well as noisy environments. The extensive simulation results using MATLAB/SIMULINK demonstrate that the new architectures overcome the limitations they addressed and the overall results confirmed significant improvements in performance compared to the conventional TDTL system

Tanlock loop noise reduction using an optimised phase detector

This article proposes a time-delay digital tanlock loop (TDTL), which uses a new phase detector (PD) design that is optimised for noise reduction making it amenable for applications that require wide lock range without sacrificing the level of noise immunity. The proposed system uses an improved phase detector design which uses two phase detectors; one PD is used to optimise the noise immunity whilst the other is used to control the acquisition time of the TDTL system. Using the modified phase detector it is possible to reduce the second- and higher-order harmonics by at least 50% compared with the conventional TDTL system. The proposed system was simulated and tested using MATLAB/Simulink using frequency step inputs and inputs corrupted with varying levels of harmonic distortion. A hardware prototype of the system was implemented using a field programmable gate array (FPGA). The practical and simulation results indicate considerable improvement in the noise performance of the proposed system over the conventional TDTL architecture

Time delay digital tanlock loop with acquisition-aided circuits

This paper proposes acquisition enhancement circuit topologies for the time delay digital tanlock loop (TDTL), which are based on feedforward (FF) and feedback (FB) control schemes. Both schemes improve the acquisition speed of the conventional TDTL by employing an auxiliary circuit. The ultimate objective of the FB and FF techniques is to control the damping ratio so as to prevent overshoot, which may cause oscillations. However, the FF topology, which uses an adaptive threshold as opposed to a fixed threshold in the FB scheme, provides better control and improved response. The performances of the proposed FF and FB mechanisms have been investigated and the results under various operating conditions are presented in this work. In addition to that, all systems were tested using FSK, FM and with a high dynamic channel for different Doppler shifts. The results indicate that it is possible to bring the system into the steady state preventing continuous oscillations whenever the system is thrown outside its locking range. Furthermore, within the locking range, cyclic-slipping was also prevented with the aid of the auxiliary circuit

Analysis and optimisation of the convergence behaviour of the single channel digital tanlock loop

The mathematical analysis of the convergence behaviour of the first-order single channel digital tanlock loop (SC-DTL) is presented. This article also describes a novel technique that allows controlling the convergence speed of the loop, i.e. the time taken by the phase-error to reach its steady-state value, by using a specialised controller unit. The controller is used to adjust the convergence speed so as to selectively optimise a given performance parameter of the loop. For instance, the controller may be used to speed up the convergence in order to increase the lock range and improve the acquisition speed. However, since increasing the lock range can degrade the noise immunity of the system, in a noisy environment the controller can slow down the convergence speed until locking is achieved. Once the system is in lock, the convergence speed can be increased to improve the acquisition speed. The performance of the SC-DTL system was assessed against similar arctan-based loops and the results demonstrate the success of the controller in optimising the performance of the SC-DTL loop. The results of the system testing using MATLAB/Simulink simulation are presented. A prototype of the proposed system was implemented using a field programmable gate array module and the practical results are in good agreement with those obtained by simulation

Initialization for time delay digital tanlock loop

This paper presents an improved second-order time delay digital tanlock loop (TDTL) system. It uses an initialization technique to enhance some of the main performance parameters of the original TDTL loop and hence overcome some of the inherent loop limitations. A one-bit Sigma-Delta modulator is used to initialize the DCO (digital controlled oscillator) for coarse tuning mode in order to enhance the noise immunity of the TDTL loop. An evaluation of the improved architecture using Simulink/Matlab, under noise-free as well as noisy conditions, demonstrated marked improvements in performance compared to the original TDTL