Application Design Trajectory towards Reusable Coprocessors MPEG Case Study

This paper presents a structured application design trajectory to transform media-processing applications— modeled as Kahn process network—into a set of functionspecific hardware units called coprocessors. The proposed design trajectory focuses on identifying hardwareimplementable computation kernels that are common for a predetermined set of applications. The design trajectory is exercised in a case study that maps MPEG video decoding and encoding applications onto a set of coprocessors in a heterogeneous multiprocessor architecture. The resulting set of coprocessors can simultaneously perform both encoding and decoding functions for multiple MPEG-2 streams in an estimated 4 mm 2 (excluding memory) in 0.18µ technology 1

An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration

Abstract—In this paper, we present a network interface (NI) for an on-chip network. Our NI decouples computation from communication by offering a shared-memory abstraction, which is independent of the network implementation. We use a transactionbased protocol to achieve backward compatibility with existing bus protocols such as AXI, OCP, and DTL. Our NI has a modular architecture, which allows flexible instantiation. It provides both guaranteed and best-effort services via connections. These are configured via NI ports using the network itself, instead of a separate control interconnect. An example instance of this NI with four ports has an area of 0.25 mmP after layout in 0.13- m technology, and runs at 500 MHz. Index Terms—Best-effort communication, communication protocols, network interfaces, networks on chip, packet switching, performance guarantees. I

C-HEAP: A Heterogeneous Multi-processor Architecture Template and Scalable and Flexible Protocol for the Design of Embedded Signal Processing Systems

The key issue in the design of Systems-on-a-Chip (SoC) is to trade-off efficiency against flexibility, and time to market versus cost. Current deep submicron processing technologies enable integration of multiple software programmable processors (e.g. CPUs, DSPs) and dedicated hardware components into a single cost-efficient IC. Our top-down design methodology with various abstraction levels helps designing these ICs in a reasonable amount of time. This methodology starts with a high-level executable specification, and converges towards a silicon implementation. A major task in the design process is to ensure that all components (hardware and software) communicate with each other correctly. In this article, we tackle this problem in the context of the signal processing domain in two ways: we propose a modular, flexible, and scalable heterogeneous multi-processor architecture template based on distributed shared memory, and we present an efficient and transparent protocol for communication and (re)configuration. The protocol implementations have been incorporated in libraries, which allows quick traversal of the various abstraction levels, so enabling incremental design. The design decisions to be taken at each abstraction level are evaluated by means of (co-)simulation. Prototyping is used too, to verify the system's functional correctness. The effectiveness of our approach is illustrated by a design case of a multi-standard video and image codec

Title: Multi-Target Data Transfer in NoCs

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Eclipse: heterogeneous multiprocessor architecture for flexible media processing

Eclipse is a heterogeneous multiprocessor architecture for high-performance media processing, including highdefinition MPEG encoding/decoding. The scalable architecture framework concurrently executes media processing kernels in function-specific multi-tasking coprocessors and a media processor, communicating via on-chip memory. Eclipse instances combine application configuration flexibility with the efficiency of function-specific hardware. 1

Chapter 2 SERVICE-BASED DESIGN OF SYSTEMS ON CHIP AND NETWORKS ON CHIP

Abstract: We discuss why performance verification of systems on chip (SOC) is difficult, by means of an example. We identify four reasons why building SOCs with predictable performance is difficult: unpredictable resource usage, variable resource performance, resource sharing, and interdependent resources. We then introduce the concept of a service, aiming to address these problems, and describe its advantages over “ad-hoc ” approaches. Finally, we introduce the ÆTHEREAL network on chip (NOC) as a concrete example of a communication resource that implements multiple service levels