Hardware Design of Digital System with Remote-DiagnosticCapability

In this paper, a hardware design of digital systems with remote-diagnostic capability is presented. We consider a method for testing a system T(l) on a module basis with a remotely installed systems T(2). In the testing mode, we set up a system (T(l)-m,m') such that a module m of T(l) is replaced by an adapter A(1) connected to other adapter A(2) through a telephone line and the corresponding module m' of T(2) is connected to A(2). If the system (T(l)-m,m') can simulate T(1) in the absence of any faluts, then it can test m' under a self test program. The main subject of this paper is to study the conditions of the system to be testable in the above sense. At first, the remote diagnostic network based on the system in this paper, restrictions to the system configuration required to perform such a diagnosis and the operation of the diagnostic system are described. The second, the module structure to make above simulation possible is considered, representing the system configuration graphically. Finally, an example of the adapter is shown and the time consumed to diagnose is discussed. One of our results is that a sufficiently large class of synchronous digital systems with few minor conventions is testable

Modifications of an Asynchronous Ring Arbiter

Some modifications of an asynchronous ring arbiter are proposed. This arbiter is composed of a chain of cells. Each cell has one to one correspondence to a device. In the chain, there exists only one privilege to arbitrate conflicts of requests from many devices. A class of modifications is high speed arbiters, obtained by increasing the number of connecting wires between two adjacent cells. As the results, the time required for the privilege to pass through a cell decreases by about one-half compared with the original arbiter. Another class of modifications is arbiters with priority rules. They are obtained by adding a few hardware to the original arbiter. The priority order of request acknowledgements in all the cells is specified. Using above modifications, conflicts of requests in many digital systems may be feasibly arbitrated

A Method of Direct Analog Simulation Using Transistor Switches and its Applications

In the analog circuits for the systms governed by the dilfercntial equations with the coefficients which are a function of one or mOre of the dependent variables, the magnitudes of their circuit elements must be variable in accordance with the nature of the function. Such circuit elements can be realized by means of inserting or removing the additional elements with high speed switches in the analog circuits. Particularly, in the case of varying stepwise this method is effective. But as an analog circuit is regarded as a short-time or repetitive type analyzer, the above switches must be instantaneous operation. In this paper, first, it is made sure by the experiments that some of the transistor switches arc met this condition, and moreover arc very low closed resistance, very high open resistance and neglegible small voltage offsets. Next, the basic technique for the direct analog simulation usiug transistor switches is described about the simple example, i.e. the oscillatory system with varying cross-scctional surge tank. Finally, as its applications, the transient problems of these oscillatory systems arc solved by means of these analog circuits

Minimum Verification test set for combinational circuit

A sufficient condition under which a minimum verification test set (MVTS) for a combinational circuit has 2w elements is derived, where w is the maximum number of inputs on which any output depends, and an algorithm to find an NVTS with 2w elements for any CUT with up to four outputs is described</p

Proof that akers' algorithm for locally exhaustive testing gives minimum test sets of combinational circuits with up to four outputs

In this paper, we prove that Akers' test generation algorithm for the locally exhaustive testing gives a minimum test set (MLTS) for every combinational circuit (CUT) with up to four outputs. That is, we clarify that Akers' test pattern generator can generate an MLTS for such CUT</p

Dynamic Design of a Tunnel Diode Transistor Combined Circuit

The dynamic design of a tunnel-diode-transistor combined circuit and the applied pulse circuits are discussed. The combined circuit, in which a tunnel diode is connected in parallel with the collector junction of a transistor, is used. The dynamic design procedure is considerably simplified by describing the transient behavior of a tunnel diode with a set of approximate expressions and by the help of a selfanalog simulator. This circuit is capable of carrying out both memory and majority logic operations, and serves as a basic unit for several different pulse circuits, such as a mcnostable circuit, a frequency divider, a ring counter, etc

Considerations of Linkages between Analog and Digital for Function x(n)

This paper describes a method of hybrid computation for the problems including the function x(n). And the greater part of it is devoted to the considerations of the linkages between the analog and the digital for the function x(n). Here the function x(n) appears frequently in the form of x(2) or x(4) in the industrial problems. As is well known the function x(2) is the characteristic included in fluid-flow problems, and x(4) is in heat-radiation problems. The weak points of analog computation for these characteristics are in accuracy and stability, but can be compensated by making use of digital computer for these parts. In the industrial uses the exclusive digital computer is more convenient than the general-purpose one. Here the relative error of analog computation, the linkages, the number of the digital elements and their relationships are considered at the same time and as the results the reasonable method of hybrid computation is obtained. That is, the exclusive digital multiplier with a compressor and an expandor is found reasonable. Its design considerations are described in details, but it is the basic idea among others that the characteristics of the compressor and the expandor are determined so that the relative error of the signal appearing at the output of the latter may be constant and as the results the necessary and sufficient number of the digital elements may be decreased. And in practice these characteristics are also realized approximately by a group of the straight lines through the origin. Finally the reduced rate of the digital elements and the optimum condition of the approximation are illustrated together with an example

Improvement of detectability for CMOS floating gate defects in supply current test

We already proposed a supply current test method for detecting floating gate defects in CMOS ICs. In the method, increase of the supply current caused by defects is promoted by superposing a sinusoidal signal on the supply voltage. In this study, we propose one way to improve detectability of the method for the defects. They are detected by analyzing the frequency of supply current and judging whether secondary harmonics of the sinusoidal signal exist or not. Effectiveness of our way is confirmed by some experiments.</p

Testing for the programming circuit of LUT-based FPGAs

The programming circuit of look-up table based FPGAs consists of two shift registers, a control circuit and a configuration memory (SRAM) cell array. Because the configuration memory cell array can be easily tested by conventional test methods for RAMs, we focus on testing for the shift registers. We show that the testing can be done by using only the faculties of the programming circuit, without using additional hardware</p

An Efficient Algorithm to Determine Equivalence of Pipelined Dependency Graphs for Their Simplification

　依存性グラフに基づいた非同期式パイプライン制御回路の設計方法が提案されている．この設計法の最終段階においては，依存性グラフと縮小した依存性グラフの等価性を何度も繰返し判定することにより，簡単化した依存性グラフが得られる．しかし，この判定には多数の状態をもつオートマトンを扱うため，その計算量は極めて大きい．本論文では，この等価性判定のための新たな効率的なアルゴリズムを提案する．まず，基本操作の実行順序の半順序をコンパクトに表現するために，基本操作直結因果関係グラフ O˙ を定義する．次に，分 岐系列ごとに O˙ の高々二つの部分グラフが一致するとき，かつそのときに限り，二つの依存性グラフが等価であることを証明する．更に，等価性の判定に必要な分岐系列のサイズと数が有限であることを証明する．最後に，上述の原理を用いたアルゴリズムの計算量が従来法に比べて大幅に小さいことを示す