Electrical characteristics of tunneling field-effect transistors with asymmetric channel thickness

Effects of using asymmetric channel thickness in tunneling field-effect transistors (TFET) are investigated in sub-50 nm channel regime using two-dimensional (2D) simulations. As the thickness of the source side becomes narrower in narrow-source wide-drain (NSWD) TFETs, the threshold voltage (V th) and the subthreshold swing (SS) decrease due to enhanced gate controllability of the source side. The narrow source thickness can make the band-to-band tunneling (BTBT) distance shorter and induce much higher electric field near the source junction at the on-state condition. In contrast, in a TFET with wide-source narrow-drain (WSND), the SS shows almost constant values and the V th slightly increases with narrowing thickness of the drain side. In addition, the ambipolar current can rapidly become larger with smaller thickness on the drain side because of the shorter BTBT distance and the higher electric-field at the drain junction. The on-current of the asymmetric channel TFET is lower than that of conventional TFETs due to the volume limitation of the NSWD TFET and high series resistance of the WSND TFET. The on-current is almost determined by the channel thickness of the source side.111sciescopu

Investigation of Hot-Carrier Reliability in Junctionless Polysilicon Thin-Film Transistors

We investigate hot-carrier (HC) reliability and 1/f noise characteristics in junctionless thin-film transistors (J-TFTs). The in-situ n +-doped channel polysilicon was deposited using low-temperature chemical vapor deposition (LP-CVD). Under the HC stressing, the junctionless devices show less degradation of the electrical characteristics than those of conventional inversion-mode TFTs (IM-TFTs). In order to further analyze the reliability behaviors, the low-frequency noise spectral density (Sid ) characteristics of the J-TFTs were measured and compared with the IM-TFTs. Under the HC stressing, the J-TFTs showed two order of magnitude lower noise levels due to bulk conduction and lower lateral electric field near drain region compared to the IM-TFTs.11sciescopu

Analog Figure-of-Merits Comparison of Gate Workfunction Variability and Random Discrete Dopant Between Inversion-Mode and Junctionless Nanowire FETs

The analog figure-of-merits (FOMs) of conventional inversion-mode (IM) and junctionless (JL) NanoWire Field Effect Transistor (NWFET) have been investigated, considering the gate WorkFunction Variability (WFV) and Random Discrete Dopant (RDD) using 3-dimensional (3D) TCAD simulation. While the JL-NWFET shows higher immune to WFV on analog FOMs, it can be easily affected by RDD due to higher channel doping level. On the other hand, the IM-NWFET shows stronger correlation between transconductance (g(m)) and gate capacitance (C-gg), leading to similar variation in cut-off frequency (f(t)) even though it shows larger g(m) and C-gg variation compared to JL-NWFET.11sci

Investigation of Threshold Voltage Variation under Negative-Bias Stress Condition of SiC Double-Implanted MOSFETs

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Mitigation of Grain Boundary Effect in 3D Vertical NAND Flash with Macaroni Structure

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Comparison of gate workfunction variability and random discrete dopant on analog figure-of-merits of inversion-mode and junctionless nanowire transistors

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Work function consideration in vacuum field emission transistor design

Effects of work function engineering on the electrical characteristics of nanoscale gate-all-around (GAA) vacuum field emission transistors (VFETs) is investigated using three dimensional technology computer aided design simulation. A low gate work function can be useful to reduce the threshold voltage suitable for lower power operation. As expected, the lower emitter work function GAA VFETs provide a reduced threshold voltage and an enhanced on-current due to the reduction of electron tunneling barrier height between the emitter and the vacuum channel. Even though a constant threshold voltage behavior has been observed with various collector materials, a higher collector work function can increase the tunneling barrier height nearby the collector side and mitigate carrier generation from the collector to vacuum, resulting in higher on-current with lower gate-leakage current. Published by the AVS.11sciescopu

Impact of geometrical parameters on the electrical performance of network-channel polycrystalline silicon thin-film transistors

The effects of geometrical parameters on the electrical characteristics of network-channel low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) were investigated. The grain boundary and interface trap densities were also extracted using parameters such as hole-to-hole distance, hole-branch top width, effective channel width, and area filling factor (A(F)). It was found that the electrical characteristics were largely dependent on A(F), mainly owing to reduced trap densities. However, excessive hole formation in the network-channel structure was found to increase channel resistance and decrease drain current. These results suggest that, for a given footprint device area, denser hole patterns are preferred for achieving better electrical characteristics in novel network-channel LTPS TFTs. (C) 2018 The Japan Society of Applied Physics11sciescopu